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ST24C04 Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer ST24C04
Beschreibung 4 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 16 Seiten
ST24C04 Datasheet, Funktion
ST24C04, ST25C04
ST24W04, ST25W04
4 Kbit Serial I2C Bus EEPROM
with User-Defined Block Write Protection
1 MILLION ERASE/WRITE CYCLES with
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
– 3V to 5.5V for ST24x04 versions
– 2.5V to 5.5V for ST25x04 versions
HARDWARE WRITE CONTROL VERSIONS:
ST24W04 and ST25W04
PROGRAMMABLE WRITE PROTECTION
TWO WIRE SERIAL INTERFACE, FULLY I2C
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 4
BYTES)
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
This specification covers a range of 4 Kbits I2C bus
EEPROM products, the ST24/25C04 and the
ST24/25W04. In the text, products are referred to
as ST24/25x04, where "x" is: "C" for Standard
version and "W" for hardware Write Control ver-
sion.
Table 1. Signal Names
PRE
E1-E2
SDA
SCL
MODE
WC
VCC
VSS
Write Protect Enable
Chip Enable Inputs
Serial Data Address Input/Output
Serial Clock
Multibyte/Page Write Mode
(C version)
Write Control (W version)
Supply Voltage
Ground
VCC
2
E1-E2
PRE
SCL
MODE/WC*
ST24x04
ST25x04
SDA
VSS
AI00851E
Note: WC signal is only available for ST24/25W04 products.
February 1999
1/16






ST24C04 Datasheet, Funktion
ST24/25C04, ST24/25W04
Table 7. AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V or 2.5V to 5.5V)
Symbol
Alt
Parameter
Min Max Unit
tCH1CH2
tR Clock Rise Time
1 µs
tCL1CL2
tF Clock Fall Time
300 ns
tDH1DH2
tR Input Rise Time
1 µs
tDL1DL1
tCHDX (1)
tF
tSU:STA
Input Fall Time
Clock High to Input Transition
300 ns
4.7 µs
tCHCL
tHIGH
Clock Pulse Width High
4 µs
tDLCL
tHD:STA
Input Low to Clock Low (START)
4
µs
tCLDX
tHD:DAT
Clock Low to Input Transition
0 µs
tCLCH
tLOW
Clock Pulse Width Low
4.7 µs
tDXCX
tSU:DAT
Input Transition to Clock Transition
250
ns
tCHDH
tSU:STO
Clock High to Input High (STOP)
4.7
µs
tDHDL
tCLQV (2)
tBUF Input High to Input Low (Bus Free)
tAA Clock Low to Next Data Out Valid
4.7 µs
0.3 3.5 µs
tCLQX
tDH Data Out Hold Time
300 ns
fC fSCL Clock Frequency
100 kHz
tW (3)
tWR Write Time
10 ms
Notes: 1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the
maximum programming time is doubled to 20ms.
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
50ns
Input Pulse Voltages
0.2VCC to 0.8VCC
Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC
Figure 4. AC Testing Input Output Waveforms
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AI00825
DEVICE OPERATION (cont’d)
The 4 most significant bits of the device select code
are the device type identifier, corresponding to the
I2C bus definition. For these memories the 4 bits
are fixed as 1010b. The following 2 bits identify the
specific memory on the bus. They are matched to
the chip enable signals E2, E1. Thus up to 4 x 4K
memories can be connected on the same bus
giving a memory capacity total of 16 Kbits. After a
START condition any memory on the bus will iden-
tify the device code and compare the following 2
bits to its chip enable inputs E2, E1.
The 7th bit sent is the block number (one block =
256 bytes). The 8th bit sent is the read or write bit
(RW), this bit is set to ’1’ for read and ’0’ for write
operations. If a match is found, the corresponding
memory will acknowledge the identification on the
SDA bus during the 9th bit time.
6/16

6 Page









ST24C04 pdf, datenblatt
ST24/25C04, ST24/25W04
DEVICE OPERATION (cont’d)
put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-
ically incremented after each byte output. After a
count of the last memory address, the address
counter will ’roll- over’ and the memory will continue
to output data.
Acknowledge in Read Mode. In all read modes
the ST24/25x04 wait for an acknowledge during the
9th bit time. If the master does not pull the SDA line
low during this time, the ST24/25x04 terminate the
data transfer and switches to a standby state.
Figure 11. Read Modes Sequence
CURRENT
ADDRESS
READ
RANDOM
ADDRESS
READ
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
ACK
NO ACK
DEV SEL
DATA OUT
R/W
ACK
ACK
ACK
NO ACK
DEV SEL *
BYTE ADDR
DEV SEL *
DATA OUT
R/W
R/W
ACK
ACK
DEV SEL
DATA OUT 1
R/W
ACK
NO ACK
DATA OUT N
ACK
ACK
ACK
ACK
DEV SEL *
BYTE ADDR
DEV SEL *
DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI00794C
Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.
12/16

12 Page





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