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ST24W01 Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer ST24W01
Beschreibung SERIAL 1K 128 x 8 EEPROM
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 16 Seiten
ST24W01 Datasheet, Funktion
ST24/25C01, ST24C01R
ST24/25W01
SERIAL 1K (128 x 8) EEPROM
1 MILLION ERASE/WRITE CYCLES with
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
– 3V to 5.5V for ST24x01 versions
– 2.5V to 5.5V for ST25x01 versions
– 1.8V to 5.5V for ST24C01R version only
HARDWARE WRITE CONTROL VERSIONS:
ST24W01 and ST25W01
TWO WIRE SERIAL INTERFACE, FULLY I2C
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 4
BYTES)
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
ST24C/W01 are replaced by the M24C01
ST25C/W01 are replaced by the M24C01-W
ST24C01R is replaced by the M24C01-R
DESCRIPTION
This specification covers a range of 1K bits I2C bus
EEPROM products, the ST24/25C01, the
ST24C01R and the ST24/25W01. In the text, prod-
ucts are referred to as ST24/25x01, where "x" is:
"C" for Standard version and "W" for hardware
Write Control version.
Table 1. Signal Names
E0-E2
SDA
SCL
Chip Enable Inputs
Serial Data Address Input/Output
Serial Clock
MODE
WC
Multibyte/Page Write Mode
(C version)
Write Control (W version)
VCC Supply Voltage
VSS Ground
NOT FOR NEW DESIGN
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
VCC
3
E0-E2
SCL
MODE/WC*
ST24x01
ST25x01
ST24C01R
SDA
VSS
AI00839D
Note: WC signal is only available for ST24/25W01 products.
November 1997
This is information on a product still in production but not recommended for new design
1/16






ST24W01 Datasheet, Funktion
ST24/25C01, ST24C01R, ST24/25W01
Table 7. AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
Symbol
Alt
Parameter
Min Max Unit
tCH1CH2
tR Clock Rise Time
1 µs
tCL1CL2
tDH1DH2
tF Clock Fall Time
tR Input Rise Time
300 ns
1 µs
tDL1DL1
tCHDX (1)
tCHCL
tDLCL
tCLDX
tCLCH
tF
tSU:STA
tHIGH
tHD:STA
tHD:DAT
tLOW
Input Fall Time
Clock High to Input Transition
Clock Pulse Width High
Input Low to Clock Low (START)
Clock Low to Input Transition
Clock Pulse Width Low
300 ns
4.7 µs
4 µs
4 µs
0 µs
4.7 µs
tDXCX
tCHDH
tDHDL
tCLQV (2)
tSU:DAT
tSU:STO
tBUF
tAA
Input Transition to Clock Transition
Clock High to Input High (STOP)
Input High to Input Low (Bus Free)
Clock Low to Next Data Out Valid
250 ns
4.7 µs
4.7 µs
0.3 3.5 µs
tCLQX
tDH Data Out Hold Time
300 ns
fC fSCL Clock Frequency
100 kHz
tW (3)
tWR Write Time
10 ms
Notes: 1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the
maximum programming time is doubled to 20ms.
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
50ns
Input Pulse Voltages
0.2VCC to 0.8VCC
Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC
Figure 4. AC Testing Input Output Waveforms
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AI00825
DEVICE OPERATION (cont’d)
The 4 most significant bits of the device select code
are the device type identifier, corresponding to the
I2C bus definition. For these memories the 4 bits
are fixed as 1010b. The following 3 bits identify the
specific memory on the bus. They are matched to
the chip enable signals E2, E1, E0. Thus up to 8 x
1K memories can be connected on the same bus
giving a memory capacity total of 8K bits. After a
START condition any memory on the bus will iden-
tify the device code and compare the following 3
bits to its chip enable inputs E2, E1, E0.
The 8th bit sent is the read or write bit (RW), this
bit is set to ’1’ for read and ’0’ for write operations.
If a match is found, the corresponding memory will
acknowledge the identification on the SDA bus
during the 9th bit time.
6/16

6 Page









ST24W01 pdf, datenblatt
ST24/25C01, ST24C01R, ST24/25W01
Figure 10. Read Modes Sequence
CURRENT
ADDRESS
READ
RANDOM
ADDRESS
READ
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
ACK
NO ACK
DEV SEL
DATA OUT
R/W
ACK
ACK
ACK
NO ACK
DEV SEL *
BYTE ADDR
DEV SEL *
DATA OUT
R/W R/W
ACK
ACK
DEV SEL
DATA OUT 1
R/W
ACK
NO ACK
DATA OUT N
ACK
ACK
ACK
ACK
DEV SEL *
BYTE ADDR
DEV SEL *
DATA OUT 1
R/W R/W
ACK
NO ACK
DATA OUT N
AI00794C
Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.
12/16

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