PDF MT28C3212P2 Data sheet ( Hoja de datos )

Número de pieza	MT28C3212P2
Descripción	FLASH AND SRAM COMBO MEMORY
Fabricantes	MICRON
Logotipo
Hay una vista previa y un enlace de descarga de MT28C3212P2 (archivo pdf) en la parte inferior de esta página. Total 47 Páginas
No Preview Available ! FLASH AND SRAM COMBO MEMORY 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY MT28C3212P2FL MT28C3212P2NFL Low Voltage, Extended Temperature FEATURES • Flexible dual-bank architecture • Support for true concurrent operations with no latency: Read bank b during program bank a and vice versa Read bank b during erase bank a and vice versa • Organization: 2,048K x 16 (Flash) 128K x 16 (SRAM) • Basic configuration: Flash Bank a (4Mb Flash for data storage) – Eight 4K-word parameter blocks – Seven 32K-word blocks Bank b (28Mb Flash for program storage) – Fifty-six 32K-word main blocks SRAM 2Mb SRAM for data storage – 128K-words • F_VCC, VCCQ, F_VPP, S_VCC voltages1 1.65V (MIN)/1.95V (MAX) F_VCC read voltage or 1.80V (MIN)/2.20V (MAX) F_VCC read voltage 1.65V (MIN)/1.95V (MAX) S_VCC read voltage or 1.80V (MIN)/2.20V (MAX) S_VCC read voltage 1.65V (MIN)/1.95V (MAX) VCCQ or 1.80V (MIN)/2.20V (MAX) VCCQ 1.80V (TYP) F_VPP (in-system PROGRAM/ERASE) 0.0V (MIN)/2.20V (MAX) F_VPP (in-system PROGRAM/ERASE)2 12V ±5% (HV) F_VPP (production programming compatibility) • Asynchronous access time1 Flash access time: 100ns or 110ns @ 1.65V F_VCC SRAM access time: 100ns @ 1.65V S_VCC • Page Mode read access1 Interpage read access: 100ns/110ns @ 1.65V F_VCC Intrapage read access: 35ns/45ns @ 1.65V F_VCC • Low power consumption • Enhanced suspend options ERASE-SUSPEND-to-READ within same bank PROGRAM-SUSPEND-to-READ within same bank ERASE-SUSPEND-to-PROGRAM within same bank • Read/Write SRAM during program/erase of Flash • Dual 64-bit chip protection registers for security purposes • PROGRAM/ERASE cycles 100,000 WRITE/ERASE cycles per block BALL ASSIGNMENT 66-Ball FBGA (Top View) 1 A NC 2 3 4 5 6 7 8 9 10 11 NC A20 A11 A15 A14 A13 A12 F_VSS VccQ NC 12 NC B A16 A8 A10 A9 DQ15 S_WE# DQ14 DQ7 C F_WE# NC DQ13 DQ6 DQ4 DQ5 D S_VSS F_RP# DQ12 S_CE2 S_VCC F_VCC E F_WP# F_VPP A19 DQ11 DQ10 DQ2 DQ3 F S_LB# S_UB# S_OE# DQ9 DQ8 DQ0 DQ1 G A18 A17 A7 A6 A3 A2 A1 S_CE1# H NC NC F_VCC A5 A4 A0 F_CE# F_VSS F_OE# NC NC NC Top View (Ball Down) • Cross-compatible command set support Extended command set Common Flash interface (CFI) compliant NOTE: 1. These specifications are guaranteed for operation within either one of two voltage ranges, 1.65V–1.95V or 1.80V–2.20V. Use only one of the two voltage ranges for PROGRAM and ERASE operations. 2. MT28C3212P2NFL only. OPTIONS MARKING • Timing 100ns -10 110ns -11 • Boot Block Top T Bottom B • VPP1 Range 0.9V–2.2V None 0.0V–2.2V N • Operating Temperature Range Commercial Temperature (0oC to +70oC) None Extended Temperature (-40oC to +85oC) ET • Package 66-ball FBGA (8 x 8 grid) FL Part Number Example: MT28C3212P2FL-10 TET 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 1 ©2002, Micron Technology, Inc. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 1 page 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY BALL DESCRIPTIONS 66-BALL FBGA NUMBERS A3, A4, A5, A6, A7, A8, B3, B4, B5, B6, E5, G3, G4, G5, G6, G7, G8, G9, H4, H5, H6 H7 SYMBOL A0–A20 F_CE# TYPE Input Input H9 F_OE# Input C3 F_WE# Input D4 F_RP# Input E3 F_WP# Input G10 S_CE1# Input D8 S_CE2 Input F5 S_OE# Input B8 S_WE# Input F3 S_LB# Input F4 S_UB# Input B7, B9, B10, DQ0–DQ15 Input/ C7, C8, C9, Output C10, D7, E6, E8, E9, E10, F7, F8, F9, F10 DESCRIPTION Address Inputs: Inputs for the addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. Flash: A0–A20; SRAM: A0–A16. Flash Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby power mode. Flash Output Enable: Enables Flash output buffers when LOW. When F_OE# is HIGH, the output buffers are disabled. Flash Write Enable: Determines if a given cycle is a Flash WRITE cycle. F_WE# is active LOW. Reset. When F_RP# is a logic LOW, the device is in reset, which drives the outputs to High-Z and resets the WSM. When F_RP# is a logic HIGH, the device is in standard operation. When F_RP# transitions from logic LOW to logic HIGH, the device resets all blocks to locked and defaults to the read array mode. Flash Write Protect. Controls the lock down function of the flexible locking feature. SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level deselects the SRAM and reduces the power consumption to standby levels. SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level deselects the SRAM and reduces the power consumption to standby levels. SRAM Output Enable: Enables SRAM output buffers when LOW. When S_OE# is HIGH, the output buffers are disabled. SRAM Write Enable: Determines if a given cycle is an SRAM WRITE cycle. S_WE# is active LOW. SRAM Lower Byte: When LOW, it selects the SRAM address lower byte (DQ0–DQ7). SRAM Upper Byte: When LOW, it selects the SRAM address upper byte (DQ8–DQ15). Data Inputs/Outputs: Input array data on the second CE# and WE# cycle during PROGRAM command. Input commands to the command user interface when CE# and WE# are active. Output data when CE# and OE# are active. (continued on next page) 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 5 Page 2 MEG x 16 PAGE FLASH 128K x 16 SRAM COMBO MEMORY FLASH MEMORY OPERATING MODES COMMAND STATE MACHINE Commands are issued to the command state ma- chine (CSM) using standard microprocessor write tim- ings. The CSM acts as an interface between external microprocessors and the internal write state machine (WSM). The available commands are listed in Table 4, their definitions are given in Table 5 and their descrip- tions in Table 6. Program and erase algorithms are au- tomated by the on-chip WSM. Table 7 shows the CSM transition states. Once a valid PROGRAM/ERASE com- mand is entered, the WSM executes the appropriate algorithm, which generates the necessary timing sig- nals to control the device internally. A command is valid only if the exact sequence of WRITEs is completed. After the WSM completes its task, the write state ma- chine status (WSMS) bit (SR7) (see Table 9) is set to a logic HIGH level (VIH), allowing the CSM to respond to the full command set again. OPERATIONS Device operations are selected by entering a stan- dard JEDEC 8-bit command code with conventional microprocessor timings into an on-chip CSM through I/O pins DQ0–DQ7. The number of bus cycles required to activate a command is typically one or two. The first operation is always a WRITE. Control pins F_CE# and F_WE# must be at a logic LOW level (VIL), and F_OE# and F_RP# must be at logic HIGH (VIH). The second operation, when needed, can be a WRITE or a READ depending upon the command. During a READ opera- tion, control pins F_CE# and F_OE# must be at a logic LOW level (VIL), and F_WE# and F_RP# must be at logic HIGH (VIH). Table 8 illustrates the bus operations for all the modes: write, read, reset, standby, and output disable. When the device is powered up, internal reset cir- cuitry initializes the chip to a read array mode of opera- tion. Changing the mode of operation requires that a command code be entered into the CSM. For each one of the two flash memory partitions, an on-chip status register is available. These two registers allow the moni- toring of the progress of various operations that can take place on a memory bank. One of the two status registers is interrogated by entering a READ STATUS REGISTER command onto the CSM (cycle 1), specify- ing an address within the memory partition boundary, and reading the register data on I/O pins DQ0–DQ7 (cycle 2). Status register bits SR0-SR7 correspond to DQ0–DQ7 (see Table 9). COMMAND DEFINITION Once a specific command code has been entered, the WSM executes an internal algorithm, generating the necessary timing signals to program, erase, and verify data. See Table 5 for the CSM command defini- tions and data for each of the bus cycles. STATUS REGISTER The status register allows the user to determine whether the state of a PROGRAM/ERASE operation is pending or complete. The status register is monitored by toggling F_OE# and F_CE# and reading the result- ing status code on I/O pins DQ0–DQ7. The high-order I/Os (DQ8–DQ15) are set to 00h internally, so only the Table 4 Command State Machine Codes For Device Mode Selection COMMAND DQ0–DQ7 10h/40h 20h 50h 60h 70h 90h 98h B0h C0h D0h FFh CODE ON DEVICE MODE Programsetup/alternateprogramsetup Block erase setup Clear status register Protection configuration setup Read status register Read protection configuration register Readquery Program/erasesuspend Protection register program/lock Program/erase resume - erase confirm Read array 2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 11 Page

Páginas	Total 47 Páginas
PDF Descargar	[ Datasheet MT28C3212P2.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
MT28C3212P2	FLASH AND SRAM COMBO MEMORY	MICRON

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar