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PDF MC14531B Data sheet ( Hoja de datos )
| Número de pieza | MC14531B | |
| Descripción | 12-Bit Parity Tree | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14531B
12-Bit Parity Tree
The MC14531B 12–bit parity tree is constructed with MOS P–channel and
N–channel enhancement mode devices in a single monolithic structure. The
circuit consists of 12 data–bit inputs (D0 thru D11), and even or odd parity
L SUFFIX
CERAMIC
CASE 620
selection input (W) and an output (Q). The parity selection input can be
considered as an additional bit. Words of less than 13 bits can generate an
even or odd parity output if the remaining inputs are selected to contain an
even or odd number of ones, respectively. Words of greater than 12–bits can
be accommodated by cascading other MC14531B devices by using the W
P SUFFIX
PLASTIC
CASE 648
input. Applications include checking or including a redundant (parity) bit to a
word for error detection/correction systems, controller for remote digital
sensors or switches (digital event detection/correction), or as a multiple input
summer without carries.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
D SUFFIX
SOIC
CASE 751B
• All Outputs Buffered
ORDERING INFORMATION
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΕ Variable Word Length
• Diode Protection on All Inputs
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
Parameter
Value
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVDD DC Supply Voltage
– 0.5 to + 18.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin, Iout Input or Output Current (DC or Transient),
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎper Pin
± 10
Unit
V
V
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD Power Dissipation, per Package†
500 mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
– 65 to + 150
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature (8–Second Soldering)
260 _C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
TRUTH TABLE
Inputs
Output
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
Decimal
(Octal)
W D11 D10 … D2 D1 D0 Equivalent
Q*
D0 7
D1 6
D2 5
LOGIC DIAGRAM
0 0 0…0 0 0
0 0 0…0 0 1
0 0 0…0 1 0
0 0 0…0 1 1
0 0 0…1 0 0
0 0 0…1 0 1
0 0 0…1 1 0
0 0 0…1 1 1
0 (0)
1 (1)
2 (2)
3 (3)
4 (4)
5 (5)
6 (6)
7 (7)
0
1
1
0
1
0
0
1
D3 4
D4 3
*******
* * *…* * *
*******
*
*
*
*
*
*
D5
D6
D7
D8
D9
D10
D11
ODD/EVEN W
2
1
15
14
13
12
11
10
VDD = PIN 16
VSS = PIN 8
9Q
1 1 1. … 0 0 0 8184 (17770)
1 1 1 … 0 0 1 8185 (17771)
1 1 1 … 0 1 0 8186 (17772)
1 1 1 … 0 1 1 8187 (17773)
1 1 1 … 1 0 0 8188 (17774)
1 1 1 … 1 0 1 8189 (17775)
1 1 1 … 1 1 0 8190 (17776)
1 1 1 … 1 1 1 8191 (17777)
0
1
1
0
1
0
0
1
*0 = Even Parity
1 = Odd Parity
NOTE: May redefine to suit application by manipulating W and/or other
available D’s.
Q = D0 D1 D2 @@@@ D11 W
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14531B
1
1 page  
–A–
16
1
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
9
–B– P 8 PL
8 0.25 (0.010) M B S
G
–T– SEATING
PLANE
K
C
D 16 PL
0.25 (0.010) M T B S A S
R X 45_
F
MJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
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including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
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51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MOTOROLA CMOS LOGIC D◊ATA
*MC14531B/D*MCM1C4513415B3/1DB
5
5 Page | ||
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| PDF Descargar | [ Datasheet MC14531B.PDF ] | |
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