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GE28F128W30BD70 Schematic ( PDF Datasheet ) - Intel

Teilenummer GE28F128W30BD70
Beschreibung (GE28Fxxx Series) Wireless Flash Memory
Hersteller Intel
Logo Intel Logo 




Gesamt 70 Seiten
GE28F128W30BD70 Datasheet, Funktion
Intel® Wireless Flash Memory (W30)
28F640W30, 28F320W30, 28F128W30
Datasheet
Product Features
High Performance Read-While-Write/Erase
— Burst Frequency at 40 MHz
— 70 ns Initial Access Speed
— 25 ns Page-Mode Read Speed
— 20 ns Burst-Mode Read Speed
— Burst and Page Mode in All Blocks and
across All Partition Boundaries
— Burst Suspend Feature
— Enhanced Factory Programming:
3.5 µs per Word Program Time
— Programmable WAIT Signal Polarity
Flash Power
— VCC = 1.70 V – 1.90 V
— VCCQ = 2.20 V – 3.30 V
— Standby Current (0.13 µm) = 8 µA (typ.)
— Read Current = 7 mA
(4 word burst, typ.)
Flash Software
— 5 µs/9 µs (typ.) Program/Erase Suspend
Latency Time
— Intel® Flash Data Integrator (FDI) and
Common Flash Interface (CFI) Compatible
Quality and Reliability
— Operating Temperature:
–40 °C to +85 °C
— 100K Minimum Erase Cycles
— 0.13 µm ETOX™ VIII Process
— 0.18 µm ETOX™ VII Process
Flash Architecture
— Multiple 4-Mbit Partitions
— Dual Operation: RWW or RWE
— Parameter Block Size = 4-Kword
— Main block size = 32-Kword
— Top and Bottom Parameter Devices
Flash Security
— 128-bit Protection Register: 64 Unique Device
Identifier Bits; 64 User OTP Protection
Register Bits
— Absolute Write Protection with VPP at Ground
— Program and Erase Lockout during Power
Transitions
— Individual and Instantaneous Block Locking/
Unlocking with Lock-Down
Density and Packaging
— 0.13 µm: 32-, 64-, and 128-Mbit in VF BGA
Package; 64-, 128-Mbit in QUAD+ Package
— 0.18 µm: 32- and 128-Mbit Densities in VF
BGA Package; 64-Mbit Density in µBGA*
Package
— 56 Active Ball Matrix, 0.75 mm Ball-Pitch
— 16-bit Data Bus
The Intel®Wireless Flash Memory (W30) device combines state-of-the-art Intel® Flash
technology to provide the most versatile memory solution for high performance, low power,
board constraint memory applications. The W30 device offers a multi-partition, dual-operation
flash architecture that enables the device to read from one partition while programming or
erasing in another partition. This Read-While-Write or Read-While-Erase capability makes it
possible to achieve higher data throughput rates as compared to single partition devices,
allowing two processors to interleave code execution because program and erase operations can
now occur as background processes.
The W30 device incorporates a new Enhanced Factory Programming (EFP) mode to improve 12
V factory programming performance. This new feature helps eliminate manufacturing
bottlenecks associated with programming high density flash devices. Compare the EFP program
time of 3.5 µs per word to the standard factory program time of 8.0 µs per word and save
significant factory programming time for improved factory efficiency.
Additionally, the W30 device includes block lock-down and programmable WAIT signal
polarity, and is supported by an array of software tools. All these features make this product a
perfect solution for any demanding memory application.
Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the lat-
est datasheet before finalizing a design.
290702-010
May 2004






GE28F128W30BD70 Datasheet, Funktion
28F320W30, 28F640W30, 28F128W30
Revision History
Date of
Revision
09/19/00
03/14/01
04/05/02
04/24/02
10/20/02
Version
Description
-001
-002
-003
-004
-005
Original Version
28F3208W30 product references removed (product was discontinued)
28F640W30 product added
Revised Table 2, Signal Descriptions (DQ15–0, ADV#, WAIT, S-UB#, S-LB#, VCCQ)
Revised Section 3.1, Bus Operations
Revised Table 5, Command Bus Definitions, Notes 1 and 2
Revised Section 4.2.2, First Latency Count (LC2–0); revised Figure 6, Data Output
with LC Setting at Code 3; added Figure 7, First Access Latency Configuration
Revised Section 4.2.3, WAIT Signal Polarity (WT)
Added Section 4.2.4, WAIT Signal Function
Revised Section 4.2.5, Data Output Configuration (DOC)
Added Figure 8, Data Output Configuration with WAIT Signal Delay
Revised Table 13, Status Register DWS and PWS Description
Revised entire Section 5.0, Program and Erase Voltages
Revised entire Section 5.3, Enhanced Factory Programming (EFP)
Revised entire Section 8.0, Flash Security Modes
Revised entire Section 9.0, Flash Protection Register; added Table 15, Simulta-
neous Operations Allowed with the Protection Register
Revised Section 10.1, Power-Up/Down Characteristics
Revised Section 11.3, DC Characteristics. Changed ICCS,ICCWS, ICCES Specs from
18 µA to 21µA; changed ICCR Spec from 12 mA to 15 mA (burst length = 4)
Added Figure 20, WAIT Signal in Synchronous Non-Read Array Operation Wave-
form
Added Figure 21, WAIT Signal in Asynchronous Page-Mode Read Operation
Waveform
Added Figure 22, WAIT Signal in Asynchronous Single-Word Read Operation
Waveform
Revised Figure 23, Write Waveform
Revised Section 12.4, Reset Operations
Clarified Section 13.2, SRAM Write Operation, Note 2
Revised Section 14.0, Ordering Information
Minor text edits
Deleted SRAM Section
Added 128M DC and AC Specifications
Added Burst Suspend
Added Read While Write Transition Waveforms
Various text edits
Revised Device ID
Revised Write Speed Bin
Various text edits
Added Latency Count Tables
Updated Packing Ball-Out and Dimension
Various text edits
Minor text clarifications
6 Datasheet

6 Page









GE28F128W30BD70 pdf, datenblatt
Intel® Wireless Flash Memory (W30)
cells. Zero-latency locking/unlocking on any memory block provides instant and complete
protection for critical system code and data. An additional block lock-down capability provides
hardware protection where software commands alone cannot change the block’s protection status.
The device’s Command User Interface (CUI) is the system processor’s link to internal flash
memory operation. A valid command sequence written to the CUI initiates device Write State
Machine (WSM) operation that automatically executes the algorithms, timings, and verifications
necessary to manage flash memory program and erase. An internal status register provides ready/
busy indication results of the operation (success, fail, and so on).
Three power-saving features– Automatic Power Savings (APS), standby, and RST#– can
significantly reduce power consumption. The device automatically enters APS mode following
read cycle completion. Standby mode begins when the system deselects the flash memory by
de-asserting CE#. Driving RST# low produces power savings similar to standby mode. It also
resets the part to read-array mode (important for system-level reset), clears internal status registers,
and provides an additional level of flash write protection.
2.2 Memory Map and Partitioning
The W30 is divided into 4-Mbit physical partitions, which allows simultaneous RWW or RWE
operations and allows users to segment code and data areas on 4-Mbit boundaries. The device’s
memory array is asymmetrically blocked, which enables system code and data integration within a
single flash device. Each block can be erased independently in block erase mode. Simultaneous
program and erase operations are not allowed; only one partition at a time can be actively
programming or erasing. See Table 1, “Bottom Parameter Memory Map” on page 13 and Table 2,
“Top Parameter Memory Map” on page 14.
The 32-Mbit device has eight partitions, the 64-Mbit device has 16 partitions, and the 128-Mbit
device has 32 partitions. Each device density contains one parameter partition and several main
partitions. The 4-Mbit parameter partition contains eight 4-Kword parameter blocks and seven 32-
Kword main blocks. Each 4-Mbit main partition contains eight 32-Kword blocks each.
The bulk of the array is divided into main blocks that can store code or data, and parameter blocks
that allow storage of frequently updated small parameters that are normally stored in EEPROM. By
using software techniques, the word-rewrite functionality of EEPROMs can be emulated.
.
12 Datasheet

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