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PDF MC14526B Data sheet ( Hoja de datos )
| Número de pieza | MC14526B | |
| Descripción | Presettable 4-Bit Down Counters | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC14526B
Presettable 4-Bit Down
Counters
The MC14526B binary counter is constructed with MOS P–channel
and N–channel enhancement mode devices in a monolithic structure.
This device is presettable, cascadable, synchronous down counter
with a decoded “0” state output for divide–by–N applications. In
single stage applications the “0” output is applied to the Preset Enable
input. The Cascade Feedback input allows cascade divide–by–N
operation with no additional gates required. The Inhibit input allows
disabling of the pulse counting function. Inhibit may also be used as a
negative edge clock.
This complementary MOS counter can be used in frequency
synthesizers, phase–locked loops, and other frequency division
applications requiring low power dissipation and/or high noise
immunity.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Edge–Clocked Design — Incremented on Positive Transition
of Clock or Negative Transition of Inhibit
• Asynchronous Preset Enable
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
Unit
V
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10 mA
PD Power Dissipation,
per Package (Note 3.)
500 mW
TA Operating Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14526BCP
AWLYYWW
1
16
SOIC–16
DW SUFFIX
CASE 751G
14526B
AWLYYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14526B
AWLYWW
1
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14526BCP
MC14526BDW
PDIP–16
SOIC–16
2000/Box
47/Rail
MC14526BDWR2 SOIC–16 1000/Tape & Reel
MC14526BF
SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14526B/D
1 page  
VDD = –VGS
CF Q0
PE
P0 Q1
P1
P2 Q2
P3
RESET Q3
INHIBIT
CLOCK “0”
VSS
VOH
IOH
EXTERNAL
POWER
SUPPLY
Figure 1. Typical Output Source
Characteristics Test Circuit
MC14526B
VDD
CF Q0
PE
P0 Q1
P1
P2 Q2
P3
RESET Q3
INHIBIT
CLOCK “0”
VSS CL
CL
CL
CL
CL
PULSE
GENERATOR
20 ns
CLOCK
50% 90%
10%
VARIABLE
WIDTH
20 ns
VDD
VSS
50% DUTY CYCLE
Figure 3. Power Dissipation
VDD = VGS
CF Q0
PE
P0 Q1
P1
P2 Q2
P3
RESET Q3
INHIBIT
CLOCK “0”
VSS
VOL
IOL
EXTERNAL
POWER
SUPPLY
Figure 2. Typical Output Sink
Characteristics Test Circuit
DEVICE
UNDER
TEST
TEST POINT
Q or “0”
CL*
* Includes all probe and jig capacitance.
Figure 4. Test Circuit
http://onsemi.com
5
5 Page 
16
1
e
Z
D
b
0.13 (0.005) M
MC14526B
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O
9
E HE
8
LE
M_
Q1
L
DETAIL P
VIEW P
A
c
A1
0.10 (0.004)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A ––– 2.05 ––– 0.081
A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.18 0.27 0.007 0.011
D 9.90 10.50 0.390 0.413
E 5.10 5.45 0.201 0.215
e 1.27 BSC
0.050 BSC
HE 7.40 8.20 0.291 0.323
L 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0 _ 10 _ 0 _ 10 _
Q1 0.70 0.90 0.028 0.035
Z ––– 0.78 ––– 0.031
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