|
|
PDF CY7C4804V25 Data sheet ( Hoja de datos )
| Número de pieza | CY7C4804V25 | |
| Descripción | 2.5V 4K/16K/64K x 80 Unidirectional Synchronous FIFO with Bus Matching | |
| Fabricantes | Cypress | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY7C4804V25 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
CY7C4808V25
sure
CY7C4806V25C025/0251
PRELIMINARY
CY7C4804V25
2.5V 4K/16K/64K x 80 Unidirectional
Synchronous FIFO with Bus Matching
Features
• High-speed, low-power, unidirectional,
First-in First-out (FIFO) memories with bus-matching
capabilities
• 64K × 80 (CY7C4808V25)
• 16K × 80 (CY7C4806V25)
• 4K × 80 (CY7C4804V25)
• 2.5V ± 100 mV power supply
• All I/Os are 1.5V HSTL
• Individual clock frequency up to 200 MHz (5-ns
Read/Write cycle times)
• High-speed access with tA = 3.8 ns
• Bus matching on both ports: ×80, ×40, ×20, ×10
• Free-running CLKA and CLKB. Clocks may be asyn-
chronous or coincident
• Cypress standard or First-Word Fall-Through modes
• Serial and parallel programming of Almost Empty/Full
flags, each with three default values (8, 16, 64)
• Master and partial reset capability
• Retransmit capability
• Big or Little Endian format
• 288 FBGA 19 mm × 19 mm (1.0-mm ball pitch) packaging
• Width and depth expansion capability
• Fabricated using Cypress 0.21-micron CMOS technol-
ogy for optimum speed/power
Preliminary Top-level Block Diagram
CLKA
CSA
ENA
SIZE1A
SIZE2A
Port A
Control
Logic
4K/16K/64K×80
A79–0
80
Dual-ported
Memory Array
MR
PR
FF/IR
AF
FIFO
Reset
Logic
FS0/SD
FS1/SEN
Write
Pointer
Read
Pointer
Status
Flag Logic
Programmable Flag
Offset Registers
Port B
Control
Logic
CLKB
CSB
ENB
BE/FWFT
SIZE1B
SIZE2B
RT/SPM
OE
80 B79–0
TDO
EF/OR
AE
JTAG Controller
TDI TCK TMS TRST
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06028 Rev. *B
Revised December 26, 2002
1 page  
PRELIMINARY
CY7C4808V25
CY7C4806V25
CY7C4804V25
Functional Description
The CY7C480XV25 family of FIFOs is comprised of
high-speed, low-power, CMOS Synchronous (clocked) FIFO
memories, meaning both independent ports employ a
synchronous interface. All data transfers through a port are
gated to the LOW-to-HIGH transition of the clock on either port
by the enable signal. The clocks for each port are independent
of one another and can be asynchronous or coincident. The
enable for each port is arranged to provide a simple unidirec-
tional interface between microprocessors and/or buses with
synchronous control.
Two kinds of reset are available on the CY7C480XV25: Master
Reset and Partial Reset. Master Reset initializes the Read and
Write pointers to the first location of the memory array,
configures the FIFO for Big Endian or Little Endian byte
arrangement, selects the Cypress standard or First-Word
Fall-Through (FWFT) mode, and determines the configuration
of the programmable flags. The flags can be programmed
either in serial mode or in parallel mode. The FIFO also comes
with three possible default flag offset settings: 8, 16, or 64.
Partial Reset also sets the Read and Write pointers to the first
location of the memory. Unlike Master Reset, any settings
existing prior to Partial Reset (i.e., programming method and
partial flag default offsets) are retained. Partial Reset is useful
since it permits flushing of the FIFO memory without changing
any configuration settings.
The CY7C480XV25 have two modes of operation: Cypress
Standard mode or FWFT mode. In the Cypress Standard
mode, the first word written to an empty FIFO is deposited into
the memory array. A Read operation is required to access that
word (along with all other subsequent words residing in
memory). In the FWFT mode, the first word written to an empty
FIFO appears automatically on the outputs, and no Read
operation is required. Nevertheless, accessing subsequent
words does necessitate formal Read request. FWFT mode is
primarily used for cascading multiple FIFOs.
The FIFO has an EF/OR flag on port B and FF/IR flag on Port
A. The EF and FF functions are selected in the Cypress
Standard mode. EF indicates whether or not the FIFO memory
is empty. FF shows whether or not the memory is full. The IR
and OR functions are selected in the FWFT mode. IR indicates
whether or not the FIFO has memory locations available. OR
shows whether the FIFO has data available for reading or not.
It marks the presence of valid data on the outputs.
The FIFO has a programmable Almost Empty flag (AE) and a
programmable Almost Full flag (AF). AE indicates the number
of words left in the FIFO memory is at the user-defined
amount. AF indicates the number of words written into the
FIFO memory has achieved a predetermined amount.
FF/IR and AF flags are synchronized to Port A clock that writes
data into its array. EF/OR and AE flags are synchronized to
Port B clock that reads data from its array. Programmable
offsets for AE and AF are loaded in parallel via Port A or in
serial via the SD input. The Serial Programming mode (SPM)
pin makes this selection. Three default offsets setting are also
provided. The AE threshold can be set at 8, 16, or 64 locations
from the empty boundary and AF threshold can be set at 8, 16,
or 64 locations from the full boundary. All these choices are
made using the FS0 and FS1 inputs during Master Reset.
The CY7C480XV25 FIFOs are characterized for operation
from 0°C to 70°C (commercial) and –40°C to 85°C (industrial).
Selection Guide
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
CY7C480XV25-200
200
3.8
5
1.0
0.6
3.8
CY7C480XV25-166
166
4.0
6
1.5
0.6
4.0
Unit
MHz
ns
ns
ns
ns
ns
Density
Package
CY7C4808V25
64K × 80
288 FBGA
CY7C4806V25
16K × 80
288 FBGA
CY7C4804V25
4K × 80
288 FBGA
Document #: 38-06028 Rev. *B
Page 5 of 30
5 Page 
PRELIMINARY
CY7C4808V25
CY7C4806V25
CY7C4804V25
Table 1. Endian/Bus Matching Configuration[1] (continued)
Each character (“A”, “B”,..., “H”) represents 10-bit data
BE/FWFT Size 1A Size 2A Port A Size 1B Size 2B
Port B
bit#79 bit#0
1 0 x20 0 0 x80 Write to FIFO
AB
CD
EF
GF
Read from FIFO ABCDEFGH
0
1
x40 Read from FIFO
ABCD
EFGH
1 0 x20 Read from FIFO
AB
CD
EF
GH
1 1 x10 Read from FIFO
A
B
C
D
E
F
G
H
Document #: 38-06028 Rev. *B
Page 11 of 30
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C4804V25.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY7C4804V25 | 2.5V 4K/16K/64K x 80 Unidirectional Synchronous FIFO with Bus Matching | Cypress |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |