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PDF SP489A Data sheet ( Hoja de datos )
| Número de pieza | SP489A | |
| Descripción | High Speed Quad RS-485/RS-422 Line Receivers | |
| Fabricantes | Sipex | |
| Logotipo |  |
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®
SP488A and SP489A
High Speed Quad
RS-485/RS-422 Line Receivers
s High Speed Versions of Sipex's
SP488 & SP489
s 30Mbps Transmission Rates
s Quad Differential Line Receivers
s RS-485 or RS-422 Applications
s Tri–state Output Control
s 30ns Typical Receiver Propagation
Delays
s –7V to +12V Common Mode Input
Range
s 1mA Supply Current
s Single +5V Supply Operation
s Pin Compatible with SN75173,
SN75175, LTC488 and LTC489
DESCRIPTION…
The SP488A and SP489A are high speed quad differential line receivers capable of
meeting the RS-485 and RS-422 protocols while running at five times the normal
transmission rates. The SP488A and SP489A are enhanced versions of Sipex's SP488
and SP489 quad RS-485/RS-422 line receivers. The SP488A features a common
receiver enable control; the SP489A provides independent receiver enable controls for each
pair of receivers. Both feature tri–state outputs and wide common–mode input range.
The receivers have a fail–safe feature which forces a logic “1” output when receiver inputs
are left floating. Both are available in 16–pin plastic DIP and SOIC packages.
RI1B 1
RI1A 2
RO1 3
EN 4
RO2 5
RI2A 6
RI2B 7
GND 8
1
2
SP488A/489ADS/07
SP488A 16 VCC
15 RI4B
RI1B 1
RI1A 2
4 14 RI4A RO1 3
13 RO4
EN1/EN2 4
12 EN
RO2 5
11 RO3
RI2A 6
3
10 RI3A
RI2B 7
9 RI3B
GND 8
1
2
SP489A 16 VCC
15 RI4B
4 14 RI4A
13 RO4
12 EN3/EN4
11 RO3
3 10 RI3A
9 RI3B
SP488A/489A High Speed Quad RS-485/RS-422 Line Receivers
1
© Copyright 2000 Sipex Corporation
1 page  
A
DI DRIVER
B
1/4 SP486
50pF EN
54Ω
RCVR
50pF
EN
1/4 SP488
ROn
CL
Figure 3. Timing Test Circuit
RCVR
CL
S1
1kΩ
S2
1kΩ
VCC
Figure 4. Enable/Disable Timing Test Circuit
SP489A PINOUT
Pin 1 — RI1B — Receiver 1 input B.
Pin 2 — RI1A — Receiver 1 input A.
Pin 3 — RO1 — Receiver 1 Output — If Re-
ceiver 1 output is enabled, if RI1A > RI1B by
200mV, Receiver output is high. If Receiver 1
output is enabled, and if RI A< RI B by 200mV,
11
Receiver 1 output is low.
Pin 4 — EN1/EN2 — Receiver 1 and 2 Output
Enable. Please refer to SP489A Truth Table (2).
Pin 5 — RO2 — Receiver 2 Output — If Re-
ceiver 2 output is enabled, if RI2A > RI2B by
200mV, Receiver 2 output is high. If Receiver 2
output is enabled, and if RI2A < RI2B by
200mV, Receiver 2 output is low.
Pin 6 — RI A — Receiver 2 input A.
2
Pin 7 — RI2B — Receiver 2 input B.
Pin 8 — GND — Digital Ground.
Pin 9 — RI3B — Receiver 3 input B.
Pin 10 — RI3A — Receiver 3 input A.
Pin 11 — RO — Receiver 3 Output — If
3
Receiver 3 output is enabled, if RI A > RI B by
33
200mV, Receiver 3 output is high. If Receiver 3
output is enabled, and if RI3A < RI3B by
200mV, Receiver 3 output is low.
Pin 12 — EN3/EN4 — Receiver 3 and 4 Output
Enable. Please refer to SP489A Truth Table (2).
Pin 13 — RO4 — Receiver 4 Output — If
Receiver 4 output is enabled, if RI4A > RI4B by
200mV, Receiver 4 output is high. If Receiver 4
output is enabled, and if RI A < RI B by
44
200mV, Receiver 4 output is low.
Pin 14 — RI A — Receiver 4 input A.
4
Pin 15 — RI B — Receiver 4 input B.
4
Pin 16 — Supply Voltage VCC — 4.75V ≤ VCC ≤
5.25V.
SP488A/489ADS/07
SP488A/489A High Speed Quad RS-485/RS-422 Line Receivers
5
© Copyright 2000 Sipex Corporation
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet SP489A.PDF ] | |
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