PDF 74HC164 Data sheet ( Hoja de datos )

Número de pieza	74HC164
Descripción	8-Bit Serial-Input/Parallel-Output Shift Register
Fabricantes	Motorola Semiconductors
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No Preview Available ! MOTOROLA SEMICONDUCTOR TECHNICAL DATA 8-Bit Serial-Input/ Parallel-Output Shift Register High–Performance Silicon–Gate CMOS The MC54/74HC164 is identical in pinout to the LS164. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The MC54/74HC164 is an 8–bit, serial–input to parallel–output shift register. Two serial data inputs, A1 and A2, are provided so that one input may be used as a data enable. Data is entered on each rising edge of the clock. The active–low asynchronous Reset overrides the Clock and Serial Data inputs. • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2 to 6 V • Low Input Current: 1 µA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the Requirements Defined by JEDEC Standard No. 7A • Chip Complexity: 244 FETs or 61 Equivalent Gates SERIAL A1 1 DATA 2 INPUTS A2 LOGIC DIAGRAM DATA 8 CLOCK 3 QA 4 QB 5 QC 6 QD 10 QE 11 QF 12 QG 13 QH PARALLEL DATA OUTPUTS 9 RESET PIN 14 = VCC PIN 7 = GND MC54/74HC164 Do Not Use for New Designs THIS DEVICE WILL BE SUPERCEDED BY MC54/74HC164A IN THE SECOND QUARTER OF 1996 14 1 J SUFFIX CERAMIC PACKAGE CASE 632–08 14 1 14 1 N SUFFIX PLASTIC PACKAGE CASE 646–06 D SUFFIX SOIC PACKAGE CASE 751A–03 ORDERING INFORMATION MC54HCXXXJ MC74HCXXXN MC74HCXXXD Ceramic Plastic SOIC PIN ASSIGNMENT A1 1 A2 2 QA 3 QB 4 QC 5 QD 6 GND 7 14 VCC 13 QH 12 QG 11 QF 10 QE 9 RESET 8 CLOCK FUNCTION TABLE Inputs Outputs Reset Clock A1 A2 QA QB … QH L X X X L L …L H XX No Change H H D D QAn … QGn H D H D QAn … QGn D = data input QAn – QGn = data shifted from the preceding stage on a rising edge at the clock input. 10/95 © Motorola, Inc. 1995 3–1 REV 7 1 page EXPANDED LOGIC DIAGRAM MC54/74HC164 8 CLOCK 1 A1 2 A2 RESET 9 DQ R DQ R DQ R DQ R DQ R DQ R DQ R DQ R 3 4 5 6 10 11 12 13 QA QB QC QD QE QF QG QH CLOCK A1 A2 RESET QA QB QC QD QE QF QG QH TIMING DIAGRAM High–Speed CMOS Logic Data DL129 — Rev 6 3–5 MOTOROLA 5 Page

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