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PDF 74FR900 Data sheet ( Hoja de datos )
| Número de pieza | 74FR900 | |
| Descripción | 9-Bit / 3-Port Latchable Datapath Multiplexer | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 74FR900 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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May 1992
Revised August 1999
74FR900
9-Bit, 3-Port Latchable Datapath Multiplexer
General Description
The 74FR900 is a data bus multiplexer routing any of three
9-bit ports to any other one of the three ports. Readback of
data latched from any port onto itself is also possible. The
74FR900 maintains separate control of all latch-enable,
output enable and select inputs for maximum flexibility.
PINV allows inversion of the data from the C8 to A8 or B8
path. This is useful for control of the parity bit in systems
diagnostics.
Fairchild’s 74FR25900 includes 25Ω resistors in series with
port A and B outputs. Resistors minimize undershoot and
ringing which may damage or corrupt sensitive device
inputs driven by these ports.
Features
s 9-bit data ports for systems carrying parity bits
s Readback capability for system self checks.
s Independent control lines for maximum flexibility
s Guaranteed multiple output switching and 250 pF load
delays
s Outputs optimized for dynamic bus drive capability
s PINV parity control facilitates system diagnostics
s FR25900 resistor option for driving MOS inputs such as
DRAM arrays
Ordering Code:
Order Number Package Number
Package Description
74FR900SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Description
Pin Names
LExx
OEx
PINV
S0, S1
A0–A8
B0–B8
C0–C8
Description
Latch Enable Inputs
Output Enable Inputs
Parity Invert Input
Select Inputs
Port A Inputs or 3-STATE Outputs
Port B Inputs or 3-STATE Outputs
Port C Inputs or 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS010990
www.fairchildsemi.com
1 page  
Extended AC Electrical Characteristics (Continued)
TA = 0°C to +70°C
TA = 0°C to +70°C
VCC = +5.0V
VCC = +5.0V
Symbol
Parameter
CL = 50 pF
Nine Outputs Switching
CL = 250 pF
(Note 6)
Units
(Note 5)
Min Max Min Max
tPHL
An or Bn to Cn
2.0 9.0 2.5 10.5
Cn to An or Bn
tPLH Propagation Delay
tPHL C8 to A8 or B8 (PINV HIGH)
3.5 11.0
tPLH Propagation Delay
tPHL
An to Bn, Bn to An
4.5 12.0 5.5 13.5
tPLH Propagation Delay
tPHL LEAC to Cn, LEBC to Cn
4.5 12.0 5.5 13.5
tPLH Propagation Delay
tPHL LECA to An, LECB to Bn
3.0 11.5 4.0 13.5
tPLH Propagation Delay
tPHL
S0 to Cn
3.0 11.0 3.0 14.0
tPLH Propagation Delay
tPHL
S1 to An or Bn
3.5 12.0 4.5 15.0
tPLH Propagation Delay
tPHL
PINV to A8 or B8
2.5 12.0
tPZH
tPZL
Output Enable Time
An, Cn
2.0 8.0
tPHZ
tPLZ
Output Disable Time
An, Cn
1.5 6.0
tPZH
tPZL
Output Enable Time
Bn
2.0 8.0
tPHZ
tPLZ
Output Disable Time
Bn
2.0 7.0
Note 5: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase,
i.e., all LOW-to-HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 6: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capac-
itors standard AC load. This specification pertains to single output switching only.
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74FR900.PDF ] | |
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