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28F128 Schematic ( PDF Datasheet ) - Intel

Teilenummer 28F128
Beschreibung 3 Volt Intel StrataFlash Memory
Hersteller Intel
Logo Intel Logo 




Gesamt 30 Seiten
28F128 Datasheet, Funktion
3 Volt Intel® StrataFlashMemory
28F128J3A, 28F640J3A, 28F320J3A (x8/x16)
Preliminary Datasheet
Product Features
s High-Density Symmetrically-Blocked
Architecture
128 128-Kbyte Erase Blocks (128 M)
64 128-Kbyte Erase Blocks (64 M)
32 128-Kbyte Erase Blocks (32 M)
s High Performance Interface Asynchronous
Page Mode Reads
110/25 ns Read Access Time (32 M)
120/25 ns Read Access Time (64 M)
150/25 ns Read Access Time (128 M)
s 2.7 V3.6 V VCC Operation
s 128-bit Protection Register
64-bit Unique Device Identifier
64-bit User Programmable OTP Cells
s Enhanced Data Protection Features
Absolute Protection with VPEN = GND
Flexible Block Locking
Block Erase/Program Lockout during
Power Transitions
s Packaging
56-Lead TSOP Package
64-Ball Intel® Easy BGA Package
s Cross-Compatible Command Support Intel
Basic Command Set
Common Flash Interface
Scalable Command Set
s 32-Byte Write Buffer
6 µs per Byte Effective Programming
Time
s 12.8M Total Min. Erase Cycles (128 Mbit)
6.4M Total Min. Erase Cycles (64 Mbit)
3.2M Total Min. Erase Cycles (32 Mbit)
100K Minimum Erase Cycles per Block
s Automation Suspend Options
Block Erase Suspend to Read
Block Erase Suspend to Program
Program Suspend to Read
s 0.25 µ Intel® StrataFlashMemory
Technology
Capitalizing on Intel’s 0.25 µ generation two-bit-per-cell technology, second generation Intel®
StrataFlashmemory products provide 2X the bits in 1X the space, with new features for mainstream
performance. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, these devices bring
reliable, two-bit-per-cell storage technology to the flash market segment.
Benefits include: more density in less space, high-speed interface, lowest cost-per-bit NOR devices,
support for code and data storage, and easy migration to future devices.
Using the same NOR-based ETOXtechnology as Intels one-bit-per-cell products, Intel StrataFlash
memory devices take advantage of over one billion units of manufacturing experience since 1987. As a
result, Intel StrataFlash components are ideal for code and data applications where high density and low
cost are required. Examples include networking, telecommunications, digital set top boxes, audio
recording, and digital imaging.
By applying FlashFilememory family pinouts, Intel StrataFlash memory components allow easy design
migrations from existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation
Intel StrataFlash memory (28F640J5 and 28F320J5) devices.
Intel StrataFlash memory components deliver a new generation of forward-compatible software support.
By using the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take
advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices.
Manufactured on Intel® 0.25 micron ETOXVI process technology, Intel StrataFlash memory provides
the highest levels of quality and reliability.
Notice: This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Order Number: 290667-008
April 2001






28F128 Datasheet, Funktion

6 Page









28F128 pdf, datenblatt
28F128J3A, 28F640J3A, 28F320J3A
2.0
2.1
Principles of Operation
The Intel StrataFlash memory devices include an on-chip WSM to manage block erase, program,
and lock-bit configuration functions. It allows for 100% TTL-level control inputs, fixed power
supplies during block erasure, program, lock-bit configuration, and minimal processor overhead
with RAM-like interface timings.
After initial device power-up or return from reset/power-down mode (see Section 3.0, Bus
Operationson page 7), the device defaults to read array mode. Manipulation of external memory
control pins allows array read, standby, and output disable operations.
Read array, status register, query, and identifier codes can be accessed through the CUI (Command
User Interface) independent of the VPEN voltage. VPENH on VPEN enables successful block
erasure, programming, and lock-bit configuration. All functions associated with altering memory
contentsblock erase, program, lock-bit configurationare accessed via the CUI and verified
through the status register.
Commands are written using standard micro-processor write timings. The CUI contents serve as
input to the WSM, which controls the block erase, program, and lock-bit configuration. The
internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and
margining of data. Addresses and data are internally latched during program cycles.
Interface software that initiates and polls progress of block erase, program, and lock-bit
configuration can be stored in any block. This code is copied to and executed from system RAM
during flash memory updates. After successful completion, reads are again possible via the Read
Array command. Block erase suspend allows system software to suspend a block erase to read or
program data from/to any other block. Program suspend allows system software to suspend a
program to read data from any other flash memory array location.
Data Protection
Depending on the application, the system designer may choose to make the VPEN switchable
(available only when memory block erases, programs, or lock-bit configurations are required) or
hardwired to VPENH. The device accommodates either design practice and encourages
optimization of the processor-memory interface.
When VPEN VPENLK, memory contents cannot be altered. The CUIs two-step block erase, byte/
word program, and lock-bit configuration command sequences provide protection from unwanted
operations even when VPENH is applied to VPEN. All program functions are disabled when VCC is
below the write lockout voltage VLKO or when RP# is VIL. The devices block locking capability
provides additional protection from inadvertent code or data alteration by gating erase and program
operations.
6 Preliminary

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