Datenblatt-pdf.com


28F004S5 Schematic ( PDF Datasheet ) - Intel

Teilenummer 28F004S5
Beschreibung BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY 4 / 8 / AND 16 MBIT
Hersteller Intel
Logo Intel Logo 




Gesamt 30 Seiten
28F004S5 Datasheet, Funktion
E
PRODUCT PREVIEW
BYTE-WIDE
SMART 5 FlashFile™ MEMORY FAMILY
4, 8, AND 16 MBIT
28F004S5, 28F008S5, 28F016S5
Includes Commercial and Extended Temperature Specifications
n SmartVoltage Technology
Smart 5 Flash: 5V VCC and 5V or
12V VPP
n High-Performance
4, 8 Mbit: 85 ns Read Access Time
16 Mbit: 95 ns Read Access Time
n Enhanced Data Protection Features
Absolute Protection with VPP = GND
Flexible Block Locking
Block Write Lockout during Power
Transitions
n Enhanced Automated Suspend Options
Program Suspend to Read
Block Erase Suspend to Program
Block Erase Suspend to Read
n Industry-Standard Packaging
40-Lead TSOP, 44-Lead PSOP
n High-Density 64-Kbyte Symmetrical
Erase Block Architecture
4 Mbit: Eight Blocks
8 Mbit: Sixteen Blocks
16 Mbit: Thirty-Two Blocks
n Extended Cycling Capability
100,000 Block Erase Cycles
n Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode
Decreases ICC in Static Mode
n Automated Program and Block Erase
Command User Interface
Status Register
n SRAM-Compatible Write Interface
n ETOX™ V Nonvolatile Flash
Technology
Intel’s byte-wide Smart 5 FlashFile™ memory family renders a variety of density offerings in the same
package. The 4-, 8-, and 16-Mbit byte-wide FlashFile memories provide high-density, low-cost, nonvolatile,
read/write storage solutions for a wide range of applications. Their symmetrically-blocked architecture, flexible
voltage, and extended cycling provide highly flexible components suitable for resident flash arrays, SIMMs,
and memory cards. Enhanced suspend capabilities provide an ideal solution for code or data storage
applications. For secure code storage applications, such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the 4-, 8-, and 16-Mbit FlashFile memories offer three levels
of protection: absolute protection with VPP at GND, selective hardware block locking, or flexible software
block locking. These alternatives give designers ultimate control of their code security needs.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. They come in
industry-standard packages: the 40-lead TSOP, ideal for board-constrained applications, and the rugged
44-lead PSOP. Based on the 28F008SA architecture, the byte-wide Smart 5 FlashFile memory family
enables quick and easy upgrades for designs that demand state-of-the-art technology.
June 1997
Order Number: 290597-003






28F004S5 Datasheet, Funktion
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
To protect programmed data, each block can be
locked. This block locking mechanism uses a
combination of bits, block lock-bits and a master
lock-bit, to lock and unlock individual blocks. The
block lock-bits gate block erase and program
operations, while the master lock-bit gates block
lock-bit configuration operations. Lock-bit config-
uration operations (Set Block Lock-Bit, Set Master
Lock-Bit, and Clear Block Lock-Bits commands) set
and clear lock-bits.
The status register and RY/BY# output indicate
whether or not the device is busy executing or
ready for a new command. Polling the status
register, system software retrieves WSM feedback.
The RY/BY# output gives an additional indicator of
WSM activity by providing a hardware status signal.
Like the status register, RY/BY#-low indicates that
the WSM is performing a block erase, program, or
lock-bit configuration. RY/BY#-high indicates that
the WSM is ready for a new command, block erase
is suspended (and program is inactive), program is
suspended, or the device is in deep power-down
mode.
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical ICCR current is 1 mA.
When CE# and RP# pins are at VCC, the
component enters a CMOS standby mode. Driving
RP# to GND enables a deep power-down mode
which significantly reduces power consumption,
provides write protection, resets the device, and
clears the status register. A reset time (tPHQV) is
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (tPHEL)
from RP#-high until writes to the CUI are
recognized.
1.3 Pinout and Pin Description
The family of devices is available in 40-lead TSOP
(Thin Small Outline Package, 1.2 mm thick) and
44-lead PSOP (Plastic Small Outline Package).
Pinouts are shown in Figures 2 and 3.
DQ0 - DQ 7
Output
Buffer
Input
Buffer
4-Mbit: A0 - A18 ,
8-Mbit: A0 - A19 ,
16-Mbit: A0 - A20
Input
Buffer
Address
Latch
Address
Counter
Y
Decoder
X
Decoder
Identifier
Register
Status
Register
Data
Comparator
Y Gating
4-Mbit: Eight
8-Mbit: Sixteen
16-Mbit: Thirty-Two
64-Kbyte Blocks
Command
Register
I/O Logic
VCC
CE#
WE#
OE#
RP#
Write State
Machine
Program/Erase
Voltage Switch
RY/BY#
VPP
VCC
GND
Figure 1. Block Diagram
6 PRODUCT PREVIEW

6 Page









28F004S5 pdf, datenblatt
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
E
Table 2. Bus Operations
Mode
Notes RP# CE# OE# WE# Address VPP DQ0–7 RY/BY#
Read
1,2,3 VIH or VIL VIL VIH
VHH
X
X DOUT
X
Output Disable
3 VIH or VIL VIH VIH
VHH
X
X High Z
X
Standby
3 VIH or VIH
X
X
X
X High Z
X
VHH
Deep Power-Down 4 VIL X X X X X High Z VOH
Read Identifier Codes
VIH or VIL VIL VIH
See
X Note 5 VOH
VHH Figure 5
Write
3,6,7 VIH or VIL VIH VIL
VHH
X
X DIN
X
NOTES:
1. Refer to DC Characteristics. When VPP VPPLK, memory contents can be read, but not altered.
2. X can be VIL or VIH for control and address input pins and VPPLK or VPPH1/2 for VPP. See DC Characteristics for VPPLK and
VPPH1/2 voltages.
3. RY/BY# is VOL when the WSM is executing internal block erase, program, or lock-bit configuration algorithms. It is VOH
when the WSM is not busy, in block erase suspend mode (with program inactive), program suspend mode, or deep power-
down mode.
4. RP# at GND ± 0.2V ensures the lowest deep power-down current.
5. See Section 4.2 for read identifier code data.
6. Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPP = VPPH1/2 and
VCC = VCC1/2 (see Section 6.2 for operating conditions).
7. Refer to Table 3 for valid DIN during a write operation.
12 PRODUCT PREVIEW

12 Page





SeitenGesamt 30 Seiten
PDF Download[ 28F004S5 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
28F004S3BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY 4 / 8 / AND 16 MBITIntel
Intel
28F004S5BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY 4 / 8 / AND 16 MBITIntel
Intel
28F004SCBYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4 / 8 / AND 16 MBITIntel
Intel

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche