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28F004S3 Schematic ( PDF Datasheet ) - Intel

Teilenummer 28F004S3
Beschreibung BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY 4 / 8 / AND 16 MBIT
Hersteller Intel
Logo Intel Logo 




Gesamt 30 Seiten
28F004S3 Datasheet, Funktion
E
PRELIMINARY
BYTE-WIDE
SMART 3 FlashFile™ MEMORY FAMILY
4, 8, AND 16 MBIT
28F004S3, 28F008S3, 28F016S3
Includes Commercial and Extended Temperature Specifications
n SmartVoltage Technology
Smart 3 Flash: 2.7 V or 3.3 V VCC
and 2.7 V, 3.3 V or 12 V VPP
n High-Performance
120 ns Read Access Time
n Enhanced Data Protection Features
Absolute Protection with VPP = GND
Flexible Block Locking
Block Write Lockout during Power
Transitions
n Enhanced Automated Suspend Options
Program Suspend to Read
Block Erase Suspend to Program
Block Erase Suspend to Read
n Industry-Standard Packaging
40-Lead TSOP, 44-Lead PSOP
and 40 Bump µBGA* CSP
n High-Density 64-Kbyte Symmetrical
Erase Block Architecture
4 Mbit: Eight Blocks
8 Mbit: Sixteen Blocks
16 Mbit: Thirty-Two Blocks
n Extended Cycling Capability
100,000 Block Erase Cycles
n Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode
Decreases ICC in Static Mode
n Automated Program and Block Erase
Command User Interface
Status Register
n SRAM-Compatible Write Interface
n ETOX™ V Nonvolatile Flash
Technology
Intel’s byte-wide Smart 3 FlashFile™ memory family renders a variety of density offerings in the same
package. The 4-, 8-, and 16-Mbit byte-wide FlashFile memories provide high-density, low-cost, nonvolatile,
read/write storage solutions for a wide range of applications. Their symmetrically-blocked architecture, flexible
voltage, and extended cycling provide highly flexible components suitable for resident flash arrays, SIMMs,
and memory cards. Enhanced suspend capabilities provide an ideal solution for code or data storage
applications. For secure code storage applications, such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the 4-, 8-, and 16-Mbit FlashFile memories offer three levels
of protection: absolute protection with VPP at GND, selective hardware block locking, or flexible software
block locking. These alternatives give designers ultimate control of their code security needs.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. They come in
industry-standard packages: the 40-lead TSOP, ideal for board-constrained applications, and the rugged
44-lead PSOP. Based on the 28F008SA architecture, the byte-wide Smart 3 FlashFile memory family
enables quick and easy upgrades for designs that demand state-of-the-art technology.
December 1997
Order Number: 290598-004






28F004S3 Datasheet, Funktion
BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY
E
To protect programmed data, each block can be
locked. This block locking mechanism uses a
combination of bits, block lock-bits and a master
lock-bit, to lock and unlock individual blocks. The
block lock-bits gate block erase and program
operations, while the master lock-bit gates block
lock-bit configuration operations. Lock-bit config-
uration operations (Set Block Lock-Bit, Set Master
Lock-Bit, and Clear Block Lock-Bits commands) set
and clear lock-bits.
The status register and RY/BY# output indicate
whether or not the device is busy executing or
ready for a new command. Polling the status
register, system software retrieves WSM feedback.
The RY/BY# output gives an additional indicator of
WSM activity by providing a hardware status signal.
Like the status register, RY/BY#-low indicates that
the WSM is performing a block erase, program, or
lock-bit configuration operation. RY/BY#-high
indicates that the WSM is ready for a new
command, block erase is suspended, program is
suspended, or the device is in deep power-down
mode.
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical ICCR current is 3 mA.
When CE# and RP# pins are at VCC, the
component enters a CMOS standby mode. Driving
RP# to GND enables a deep power-down mode
which significantly reduces power consumption,
provides write protection, resets the device, and
clears the status register. A reset time (tPHQV) is
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (tPHEL)
from RP#-high until writes to the CUI are
recognized.
1.3 Pinout and Pin Description
The family of devices is available in 40-lead TSOP
(Thin Small Outline Package, 1.2 mm thick), 44-
lead PSOP (Plastic Small Outline Package) and 40-
bump µBGA* CSP (28F008S3 and 28F016S3 only).
Pinouts are shown in Figures 2, 3 and 4.
DQ0 - DQ 7
Output
Buffer
Input
Buffer
4-Mbit: A0 - A18 ,
8-Mbit: A0 - A19 ,
16-Mbit: A0 - A20
Input
Buffer
Address
Latch
Address
Counter
Y
Decoder
X
Decoder
Identifier
Register
Status
Register
Data
Comparator
Y Gating
4-Mbit: Eight
8-Mbit: Sixteen
16-Mbit: Thirty-Two
64-Kbyte Blocks
Command
Register
I/O Logic
VCC
CE#
WE#
OE#
RP#
Write State
Machine
Program/Erase
Voltage Switch
RY/BY#
VPP
VCC
GND
Figure 1. Block Diagram
6 PRELIMINARY

6 Page









28F004S3 pdf, datenblatt
BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY
E
2.1 Data Protection
Depending on the application, the system designer
may choose to make the VPP power supply
switchable (available only when memory block
erase, program, or lock-bit configuration operations
are required) or hardwired to VPPH1/2. The device
accommodates either design practice and
encourages optimization of the processor-memory
interface.
When VPP VPPLK, memory contents cannot be
altered. When high voltage is applied to VPP, the
two-step block erase, program, or lock-bit
configuration command sequences provides pro-
tection from unwanted operations. All write
functions are disabled when VCC voltage is below
the write lockout voltage VLKO or when RP# is at
VIL. The device’s block locking capability provides
additional protection from inadvertent code or data
alteration by gating erase and program operations.
3.0 BUS OPERATION
The local CPU reads and writes flash memory
in-system. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
3.1 Read
Block information, identifier codes, or status register
can be read independent of the VPP voltage. RP#
can be at either VIH or VHH.
The first task is to write the appropriate read-mode
command (Read Array, Read Identifier Codes, or
Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep power-
down mode, the device automatically resets to read
array mode. Four control pins dictate the data flow
in and out of the component: CE#, OE#, WE#, and
RP#. CE# and OE# must be driven active to obtain
data at the outputs. CE# is the device selection
control, and when active enables the selected
memory device. OE# is the data output (DQ0–DQ7)
control and when active drives the selected
memory data onto the I/O bus. WE# must be at VIH
and RP# must be at VIH or VHH. Figure 17
illustrates a read cycle.
12
3.2 Output Disable
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0–DQ7 are
placed in a high-impedance state.
3.3 Standby
CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
power consumption. DQ0–DQ7 outputs are placed
in a high-impedance state independent of OE#. If
deselected during block erase, program, or lock-bit
configuration, the device continues functioning and
consuming active power until the operation
completes.
3.4 Deep Power-Down
RP# at VIL initiates the deep power-down mode.
In read mode, RP#-low deselects the memory,
places output drivers in a high-impedance state,
and turns off all internal circuits. RP# must be held
low for time tPLPH. Time tPHQV is required after
return from power-down until initial memory access
outputs are valid. After this wake-up interval,
normal operation is restored. The CUI resets to
read array mode, and the status register is set to
80H.
During block erase, program, or lock-bit
configuration, RP#-low will abort the operation.
RY/BY# remains low until the reset operation is
complete. Memory contents being altered are no
longer valid; the data may be partially erased or
written. Time tPHWL is required after RP# goes to
logic-high (VIH) before another command can be
written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase,
program, or lock-bit configuration modes. If a CPU
reset occurs with no flash memory reset, proper
CPU initialization may not occur because the flash
memory may be providing status information
instead of array data. Intel’s flash memories allow
proper CPU initialization following a system reset
through the use of the RP# input. In this application,
RP# is controlled by the same RESET# signal that
resets the system CPU.
PRELIMINARY

12 Page





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