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PDF 28C64A Data sheet ( Hoja de datos )
| Número de pieza | 28C64A | |
| Descripción | 64K (8K x 8) CMOS EEPROM | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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28C64A
64K (8K x 8) CMOS EEPROM
FEATURES
• Fast Read Access Time—150 ns
• CMOS Technology for Low Power Dissipation
- 30 mA Active
- 100 µA Standby
• Fast Byte Write Time—200 µs or 1 ms
• Data Retention >200 years
• High Endurance - Minimum 100,000 Erase/Write
Cycles
• Automatic Write Operation
- Internal Control Timer
- Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
• Data Polling
• Ready/Busy
• Chip Clear Operation
• Enhanced Data Protection
- VCC Detector
- Pulse Filter
- Write Inhibit
• Electronic Signature for Device Identification
• 5-Volt-Only Operation
• Organized 8Kx8 JEDEC Standard Pinout
- 28-pin Dual-In-Line Package
- 32-pin PLCC Package
- 28-pin Thin Small Outline Package (TSOP)
8x20mm
- 28-pin Very Small Outline Package (VSOP)
8x13.4mm
• Available for Extended Temperature Ranges:
- Commercial: 0˚C to +70˚C
DESCRIPTION
The Microchip Technology Inc. 28C64A is a CMOS 64K non-
volatile electrically Erasable PROM. The 28C64A is
accessed like a static RAM for the read or write cycles without
the need of external components. During a “byte write”, the
address and data are latched internally, freeing the micropro-
cessor address and data bus for other operations. Following
the initiation of write cycle, the device will go to a busy state
and automatically clear and write the latched data using an
internal control timer. To determine when the write cycle is
complete, the user has a choice of monitoring the Ready/
Busy output or using Data polling. The Ready/Busy pin is an
open drain output, which allows easy configuration in wired-
or systems. Alternatively, Data polling allows the user to read
the location last written to when the write operation is com-
plete. CMOS design and processing enables this part to be
used in systems where reduced power consumption and reli-
ability are required. A complete family of packages is offered
to provide the utmost flexibility in applications
PACKAGE TYPE
RDY/BSY
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
•1
2
3
4
5
6 DIP/
7
8
SOIC
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE
NC
A8 A6 5
A9 A5 6
A11 A4 7
OE A3 8
A10 A2 9
CE A1 10
I/O7 A0 11
I/O6
NC
I/O0
12
13
I/O5
I/O4
I/O3
PLCC
29 A8
28 A9
27 A11
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
• Pin 1 indicator on PLCC on top of package
OE 1
A11 2
A9 3
A8 4
NC 5
WE 6
Vcc 7
RDY/BSY 8
A12 9
A7 10
A6 11
A5 12
A4 13
A3 14
TSOP
28 A10
27 CE
26 I/07
25 I/06
24 I/05
23 I/04
22 I/03
21 Vss
20 I/02
19 I/01
18 I/00
17 A0
16 A1
15 A2
OE
A11
A9
A8
NC
WE
VCC
RDY/BSY
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
VSOP
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
14 VSS
13 I/O2
12 I/O1
11 I/O0
10 A0
9 A1
8 A2
BLOCK DIAGRAM
I/O0 I/O7
VSS
VCC
CE
OE
WE
Rdy/
Busy
A0
A12
Data Protection
Circuitry
Chip Enable/
Output Enable
Control Logic
Auto Erase/Write
Timing
Program Voltage
Generation
Data
Poll
Y
L Decoder
a
t
c
h
eX
s Decoder
Input/Output
Buffers
Y Gating
16K bit
Cell Matrix
© 1994 Microchip Technology Inc.
DS11109G-page 1
1 page  
28C64A
FIGURE 1-3: DATA POLLING WAVEFORMS
VIH
Address
VIL
VIH
CE
VIL
VIH
WE
VIL
Address Valid
t WPL
t WPH
VIH
OE
VIL
VIH
Data
VIL
t DV
Data In
Valid
t WC
FIGURE 1-4: CHIP CLEAR WAVEFORMS
VIH
CE
VIL
t ACC
t CE
Last Written
Address Valid
t OE
I/O7 Out
True Data Out
VH
OE
VIH
VIH
WE
VIL
tS tH
tW
tW = 10ms
tS = tH = 1µs
VH = 12.0V ±0.5V
TABLE 1-5: SUPPLEMENTARY CONTROL
Mode
Chip Clear
Extra Row Read
Extra Row Write
Note: VH = 12.0V±0.5V.
CE OE WE A9
VIL VIH VIL
X
VIL VIL VIH A9 = VH
* VIH * A9 = VH
*Pulsed per programming waveforms.
VCC
VCC
VCC
VCC
I/OI
Data Out
Data In
© 1994 Microchip Technology Inc.
DS11109G-page 5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 28C64A.PDF ] | |
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