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SN74LS193 Schematic ( PDF Datasheet ) - Motorola Semiconductors

Teilenummer SN74LS193
Beschreibung PRESETTABLE 4-BIT BINARYUP/DOWN COUNTER
Hersteller Motorola Semiconductors
Logo Motorola Semiconductors Logo 




Gesamt 9 Seiten
SN74LS193 Datasheet, Funktion
PRESETTABLE BCD/DECADE
UP/DOWN COUNTER
PRESETTABLE 4-BIT BINARY
UP/DOWN COUNTER
The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the
SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate
Count Up and Count Down Clocks are used and in either counting mode the
circuits operate synchronously. The outputs change state synchronous with
the LOW-to-HIGH transitions on the clock inputs.
Separate Terminal Count Up and Terminal Count Down outputs are
provided which are used as the clocks for a subsequent stages without extra
logic, thus simplifying multistage counter designs. Individual preset inputs
allow the circuits to be used as programmable counters. Both the Parallel
Load (PL) and the Master Reset (MR) inputs asynchronously override the
clocks.
Low Power . . . 95 mW Typical Dissipation
High Speed . . . 40 MHz Typical Count Frequency
Synchronous Counting
Asynchronous Master Reset and Parallel Load
Individual Preset Inputs
Cascading Circuitry Internally Provided
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC P0 MR TCD TCU PL P2 P3
16 15 14 13 12 11 10 9
1 2 3 4 56 78
P1 Q1 Q0 CPD CPU Q2 Q3 GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
PIN NAMES
LOADING (Note a)
HIGH
LOW
CPU
CPD
MR
Count Up Clock Pulse Input
Count Down Clock Pulse Input
Asynchronous Master Reset (Clear) Input
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
PL Asynchronous Parallel Load (Active LOW) Input 0.5 U.L. 0.25 U.L.
Pn
Qn
TCD
TCU
Parallel Data Inputs
Flip-Flop Outputs (Note b)
Terminal Count Down (Borrow) Output (Note b)
Terminal Count Up (Carry) Output (Note b)
0.5 U.L.
10 U.L.
10 U.L.
10 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
SN54/74LS192
SN54/74LS193
PRESETTABLE BCD/ DECADE
UP/ DOWN COUNTER
PRESETTABLE 4-BIT BINARY
UP/ DOWN COUNTER
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
11 15 1 10 9
5
PL P0 P1 P2 P3
CPU TCU
12
4
CPD
MR Q0 Q1
Q2
Q3TCD
13
14 3 2 6 7
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-351






SN74LS193 Datasheet, Funktion
SN54/74LS192 SN54/74LS193
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW
ts
th
trec
Parameter
Any Pulse Width
Data Setup Time
Data Hold Time
Recovery Time
Limits
Min Typ Max
20
20
5.0
40
Unit
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
DEFINITIONS OF TERMS
SETUP TIME (ts) is defined as the minimum time required for
the correct logic level to be present at the logic input prior to the
PL transition from LOW-to-HIGH in order to be recognized and
transferred to the outputs.
HOLD TIME (th) is defined as the minimum time following the
PL transition from LOW-to-HIGH that the logic level must be
maintained at the input in order to ensure continued recogni-
tion. A negative HOLD TIME indicates that the correct logic
level may be released prior to the PL transition from
LOW-to-HIGH and still be recognized.
RECOVERY TIME (trec) is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH data to the Q outputs.
FAST AND LS TTL DATA
5-356

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