|
|
PDF LTC1390 Data sheet ( Hoja de datos )
| Número de pieza | LTC1390 | |
| Descripción | 8-Channel Analog Multiplexer with Serial Interface | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LTC1390 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
|
No Preview Available !
FEATURES
s 3-Wire Serial Digital Interface
s Data Retransmission Allows Series Connection
with Serial A/D Converters
s Single 3V to ±5V Supply Operation
s Analog Inputs May Extend to Supply Rails
s Low Charge Injection
s Low RON: 75Ω Max
s Low Leakage: ±5nA Max
s Guaranteed Break-Before-Make
s TTL/CMOS Compatible for All Digital Inputs
s Cascadable to Allow Additional Channels
s Can Be Used as a Demultiplexer
APPLICATI S
s Data Acquisition Systems
s Communication Systems
s Signal Multiplexing/Demultiplexing
LTC1390
8-Channel
Analog Multiplexer
with Serial Interface
DESCRIPTIO
The LTC®1390 is a high performance CMOS 8-to-1 analog
multiplexer. It features a 3-wire digital interface with a
bidirectional data retransmission feature, allowing it to be
wired in series with a serial A/D converter while using only
one serial port. The interface also allows several LTC1390s
to be wired in series or parallel, increasing the number of
MUX channels available using only a single digital port. All
the above features are also valid when LTC1390 operates
as a demultiplexer such as with a D/A converter.
The LTC1390 features a typical RON of 45Ω, typical switch
leakage of 50pA, and guaranteed break-before-make op-
eration. Charge injection is ±10pC maximum. All digital
inputs are TTL and CMOS compatible when operated from
single or dual supplies. The inputs can withstand 100mA
fault currents.
The LTC1390 is available in 16-pin PDIP and narrow SO
packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATI
VCC VEE
ANALOG
INPUTS
1 S0
V + 16
2
S1
15
D
3 S2 LTC1390 V – 14
4 S3
DATA 2 13
5 S4
DATA 1 12
6 S5
CS 11
7 S6
CLK 10
8 S7
GND 9
3-WIRE
SERIAL
INTERFACE
TO MUX AND ADC
DATA
CLK
CS
OPTIONAL A/D
INPUT FILTER
VCC
1
CS
8
VCC
2
+IN
7
CLK
3 LTC1096
6
–IN DOUT
4
GND
5
VREF
VCC
47k
LTC1390 • TA01
ON-Resistance vs
Analog Input Voltage
250
TA = 25°C
200
V+ = 3V
V – = 0V
150
100
V+ = 5V
50 V – = – 5V
0
–5 –4 –3 –2 –1 0 1 2 3 4 5
ANALOG INPUT VOLTAGE, VS (V)
LTC1390 • TA02
1
1 page  
LTC1390
PIN FUNCTIONS
S0 to S7 (Pins 1 to 8): Analog Multiplexer Inputs/Analog
Demultiplexer Outputs.
GND (Pin 9): Digital Ground. Connect to system ground.
CLK (Pin 10): System Clock (TTL/CMOS Compatible). The
clock synchronizes the channel selection bits and the
serial data transfer from Data 1 to Data 2.
CS (Pin 11): Chip Select Input (TTL/CMOS Compatible). A
logic high on this input enables LTC1390 to read in the
channel selection bits and allow data transfer from Data 1
to Data 2. A logic low enables the desired channel for
analog signal transmission and allows data transfer from
Data 2 to Data 1.
Data 1 (Pin 12): Bidirectional Digital Input/Output (TTL/
CMOS Compatible). Input for the channel selection bits.
Data 2 (Pin 13): Bidirectional Digital Input/Output (TTL/
CMOS Compatible).
V – (Pin 14): Negative Supply.
D (Pin 15): Analog Multiplexer Output/Analog
Demultiplexer Input.
V+ (Pin 16): Positive Supply.
UU W U
APPLICATIO S I FOR ATIO
Multiplexer Operation
Figure 1 shows the block diagram of the components
within the LTC1390 required for MUX operation. The
LTC1390 uses Data 1 to select its 8 channels and a chip
select input CS to switch on the selected channel as shown
in Figure 2.
CLK
DATA 1
CS
CONTROL
LOGIC
4-BIT SHIFT
REGISTER
ANALOG
INPUT
MUX
BLOCK
ANALOG
OUTPUT
LTC1390 • F01
Figure 1: Simplified Block Diagram of the MUX Operation
When CS is high, the input data on the Data 1 pin is latched
into the 4-bit shift register on each rising clock edge. The
input data consists of an “EN” bit and a string of three bits
for channel selection. If “EN” bit is logic high as illustrated
in the first input data sequence, it enables the selected
channel. To ensure correct operation, the CS must be
pulled low before the next rising clock edge.
Once the CS is pulled low, all channels are simultaneously
switched off to ensure a break-before-make interval. After
a delay of tON, the selected channel is switched on allowing
signal transmission. The selected channel remains on
until the next falling edge of CS, and after a delay of tOFF,
it terminates the analog signal transmission and subse-
quently allows the selection of the next channel. If “EN” bit
is logic low, as illustrated in the second data sequence, it
disables all channels and there will be no analog signal
CLK
CS
DATA 1
ANY
ANALOG
INPUTS
D
EN = HIGH
B2
B1 B0
EN = LOW
B2 B1 B0
tON
Figure 2: Multiplexer Operation
tOFF
LTC1390 • F02
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet LTC1390.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LTC1390 | 8-Channel Analog Multiplexer with Serial Interface | Linear Technology |
| LTC1390CN | 8-Channel Analog Multiplexer with Serial Interface | Linear Technology |
| LTC1390CS | 8-Channel Analog Multiplexer with Serial Interface | Linear Technology |
| LTC1391 | 8-Channel Analog Multiplexer with Cascadable Serial Interface | Linear Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |