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S93662 Schematic ( PDF Datasheet ) - ETC

Teilenummer S93662
Beschreibung Voltage Monitor and Reset Controller
Hersteller ETC
Logo ETC Logo 




Gesamt 14 Seiten
S93662 Datasheet, Funktion
SUMMIT
MICROELECTRONICS, Inc.
Precision Supply-Voltage Monitor and Reset Controller
S93662/S93663
FEATURES
• Precision Monitor & RESET Controller
— RESET and RESET Outputs
— Guaranteed RESET Assertion to VCC = 1V
— 200ms Reset Pulse Width
— Internal 1.26V Reference with ±1% Accuracy
— ZERO External Components Required
• Memory
— 4K-bit Microwire Memory
— S93662
– Internally Ties ORG Low
– 100% Compatible With all 8-bit
Implementations
– Sixteen Byte Page Write Capability
— S93663
– Internally Ties ORG High
– 100% Compatible With all 16-bit
Implementations
– Eight Word Page Write Capability
OVERVIEW
The S93662 and S93663 are precision power supervi-
sory circuits providing both active high and active low
reset outputs.
Both devices have 4k-bits of E2PROM memory that is
accessible via the industry standard microwire bus. The
S93662 is configured with an internal ORG pin tied low
providing a 8-bit byte organization and the S93663 is
configured with an internal ORG pin tied high providing
a 16-bit word organization. Both the S93662 and
S93663 have page write capability. The devices are
designed for a minimum 100,000 program/erase cycles
and have data retention in excess of 100 years.
BLOCK DIAGRAM
VCC
8
5kHz
OSCILLATOR
RESET
PULSE
GENERATOR
6 RESET#
CS 1
SK 2
DI 3
+ VTRIP
RESET
CONTROL
1.26V
MODE
DECODE
ADDRESS
DECODER
WRITE
CONTROL
7 RESET
DO 4
5
GND
DATA I/O
E2PROM
MEMORY
ARRAY
2012 T BD 2.0
SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com
© SUMMIT MICROELECTRONICS, Inc. 2000
2012 2.0 4/18/00
Characteristics subject to change without notice
1






S93662 Datasheet, Funktion
S93662/S93663
SK
CS
DI
1
00
10
STATUS VERIFY
tCS
STANDBY
HIGH-Z
DO
tSV
BUSY
t EW
READY
t HZ
HIGH-Z
Figure 6. ERAL Instruction Timing
2012 ILL 8 1.0
SK
CS
DI 1 0 0 0 1
DO
STATUS VERIFY
tCS
STANDBY
DN DO
tSV
BUSY
t EW
READY
t HZ
HIGH-Z
Figure 7. WRAL Instruction Timing
2012 ILL 10 1.0
INSTRUCTION SET
Instruction
Start
Bit
READ
1
ERASE
1
WRITE
1
EWEN
1
EWDS
1
ERAL
1
WRAL
1
Opcode
Address
x8 x16
10 A8A0 A7A0
11 A8A0 A7A0
01 A8A0 A7A0
00 11xxx xxxx 11xxx xxx
00 00xxx xxxx 00xxx xxx
00 10xxx xxxx 10xxx xxx
00 01xxx xxxx 01xxx xxx
Data
x8
D7D0
D7D0
x16
D15D0
D15D0
Comments
Read Address ANA0
Clear Address ANA0
Write Address ANA0
Write Enable
Write Disable
Clear All Addresses
Write All Addresses
2012 PGM T5 1.1
2012 2.0 4/18/00
6

6 Page









S93662 pdf, datenblatt
S93662/S93663
Ready/Busy Status
During the internal write operation the S93662/663 memory array is inaccessible. After starting the write operation
(taking CS low) the host can implement a 10ms time-out routine or alternatively it can employ a polling routine that tests
the state of the DO pin.
After starting the write, testing for the status is easily accomplished by taking CS high and testing the state of DO. If
it is low the device is still busy with the internal write. If it is high the write operation has completed.
For the polling routine the host has the option of toggling CS for each test of DO, or it can place CS high and then
intermittently test DO. SK is not required for any of these operations. Once the device is ready, it will continue to drive
DO high whenever the S93662/663 is selected. The ready state of DO can be cleared by clocking in a start bit; this
start bit can either be the beginning of a new command sequence or it can be a dummy start bit with CS returning low
before the host issues a new command.
SK
CS
STATUS VERIFY
tCS
DI
tSV tHZ
DO
BUSY READY
HIGH-Z
HIGH-Z
t EW
STATUS CLEARED
2012 ILL 13 1.0
2012 2.0 4/18/00
12

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