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OXFW911 Schematic ( PDF Datasheet ) - ETC

Teilenummer OXFW911
Beschreibung IEEE1394 to ATA/ATAPI Native Bridge
Hersteller ETC
Logo ETC Logo 




Gesamt 30 Seiten
OXFW911 Datasheet, Funktion
FEATURES
S400 (50 Mbytes/s) compliant 1394-1995 Link and
Transaction layers
Compatible with 1394-1995 and 1394A Phys.
Microsoft Win98-Second Edition, Win2000 and Apple
MacOS generic driver support
SBP-2 Target Revision 4 compliant interface
Fully ATA-5 compliant (see T13-1321D)
Support for UDMA5 (ATA100)
Sustained data transfer of 35 MB/s
Supports PIO modes 0 to 4, DMA modes 0 to 2 and
Ultra DMA modes 0 to 5
ORB co-processor to accelerate translation of ORBs
to ATAPI commands
Supports ORB chaining for increased performance
DESCRIPTION
The OXFW911 is a high-performance 1394 to
ATA/ATAPI (IDE) native bridge with an integrated target
Serial Bus Protocol (SBP-2 ) controller. By supporting
the SBP-2 protocol, the device can use generic SBP-2
drivers available in the Microsoft Windows 98SE, Microsoft
Windows 2000, Microsoft Millennium and Apple MacOS
(8.4 to 9.04) operating systems. MacOS support also
includes booting from Firewire disk.
The device is ideally suited for smart-cable or tailgate
interface applications for removable-media drives, compact
flash card readers, CD-ROM, CD-R, CD-RW, DVD-ROM,
DVD-RAM and hard disk drives, allowing IDE drives to be
connected to a 1394 serial bus in a plug-and-play fashion.
Both ATA and ATAPI devices are supported using the
same firmware.
This highly integrated device offers a two-chip solution to
native bridge applications using an external 1394 PHY. The
device is compatible with both 1394-1995 and 1394A
PHYs.
The LINK controller complies with 1394-1995 and 1394A
specifications. The 1394 transaction layer and SBP-2
protocol is implemented using a combination of the
ARM7TDMI (low-power 32-bit RISC processor), an ORB
(Operational Request Block) hardware co-processor and a
high performance buffer manager.
The buffer manager has a RAM bandwidth of 800Mbps. It
provides storage for 1394 and ATA/ATAPI packets,
OXFW911
IEEE1394 to ATA/ATAPI Native Bridge
Data Sheet
High performance ATA command translation in
firmware using Reduced Block Command (RBC) set
Integrated 32-bit RISC processor (ARM7TDMI) with
on-chip scratch RAM
Optional External Serial ROM interface for
configuration data, user serial number, etc.
Integrated 512kb Flash memory
Blank Flash memory programming feature via 1394
bus
Firmware and Flash Programming Utilities supplied by
Oxford Semiconductor
3.3 Volts operation
Low Power CMOS
Ultra-thin 128-TQFP package (14 x 14 x 1 mm)
automatically storing them and passing them to the
appropriate destinations, without any intervention from the
processor. It also provides storage and manages the
sequencing of ORB fetching to reduce latency and improve
data throughput.
The configuration data including the IEEE OUI
(Organisational Unique Identifier) and device serial number
is stored in the Flash ROM which may be uploaded from
the 1394 bus, even when blank. The device also facilitates
firmware uploads from the 1394 bus.
The ORB co-processor translates ORBs as defined in the
SBP-2 protocol into ATA/ATAPI commands, and
automatically stores error/status messages at an address
specified by the host.
Concurrent operation of the ATA/ATAPI and 1394
interfaces are facilitated using the high throughput buffer
manager where LINK, ATAPI manager and ARM7TDMI
can perform interleaved accesses to the on-chip RAM
buffer. The high performance processor ensures that no
significant latency is incurred. The ATA command
translation is performed in firmware to meet RBC (Reduced
Block Commands) standard, T10-1228D. The ATA/ATAPI
Manager supports PIO modes 0 to 4, DMA modes 0 to 2
and Ultra DMA mode 0 to 5 and provides the interface to
the IDE bus. It is compliant with T13-1321D, ATA-5
specification, as well as support for ATA100.
Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141
© Oxford Semiconductor 2001
OXFW911 Data Sheet Revision 1.1 – Mar 2001
Part No. OXFW911-TQ-A






OXFW911 Datasheet, Funktion
OXFORD SEMICONDUCTOR LTD.
OXFW911
14, 7, 39, 47, 55, 67, 75, 93, 96,
106, 112,
29, 25, 26, 83, 87, 118
Other
1, 122
GND AC GND
GND DC GND
NC
Supplies GND to output buffers in switching (AC) state
Ground (0 volts). Supplies GND to core logic, input buffers
and output buffers in steady state
No Connect
Note 1: Direction key:
I Input
IU Input with internal pull-up
ID Input with external pull-down
O Output
I/O Bi-directional
T_I 5V tolerant input
Table 1: Pin Descriptions
T_O
T_I/O
GND
VDD
NC
5V tolerant output
5V tolerant bi-directional
Ground
3.3V power
No Connect
Note 2: Power & Ground
There are two GND and two VDD rails internally. One set of rails supply power and ground to output buffers while in switching
state (called AC power) and another rail supply the core logic, input buffers and output buffers in steady-state (called DC rail).
The rails are not connected internally. This precaution reduces the effects of simultaneous switching outputs and undesirable RF
radiation from the chip.
Data Sheet Rev 1.1
Page 6

6 Page









OXFW911 pdf, datenblatt
OXFORD SEMICONDUCTOR LTD.
6.2 1394 Link-Phy interface
The timings for 1394 Link – Phy are shown below :
Symbol
tlsu
tlh
Tld1
Tld2
Tld3
tcyc
Parameter
Setup Time, PD[7:0] and CTL[1:0] before PhyClk
Hold Time, PD[7:0] and CTL[1:0] after PhyClk
Delay Time, PhyClk input high to initial instance of PD[7:0], CTL[1:0]
and Lreq outputs valid
Delay Time, PhyClk input high to subsequent instance(s) of PD[7:0],
CTL[1:0] and Lreq outputs valid
Delay Time, PhyClk input high to PD[7:0], CTL[1:0] and Lreq outputs
invalid (high impedance)
Duty Cycle
Table 8: OXFW911 Link-Phy interface timings
Min
8
0
2
2
2
45
OXFW911
Max Units
ns
ns
10 ns
10 ns
10 ns
55 %
Data Sheet Rev 1.1
Page 12

12 Page





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