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PDF ORT82G5 Data sheet ( Hoja de datos )
| Número de pieza | ORT82G5 | |
| Descripción | ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC | |
| Fabricantes | Agere Systems | |
| Logotipo |  |
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Preliminary Data Sheet
July 2001
ORCA® ORT82G5 1.0—1.25/2.0—2.5/3.125 Gbits/s
Backplane Interface FPSC
Introduction
Agere Systems Inc. has developed a next generation
FPSC intended for high-speed serial backplane data
transmission. Built on the Series 4 reconfigurable
embedded system-on-chips (SoC) architecture, the
ORT82G5 is made up of backplane transceivers con-
taining eight channels, each operating at up to
3.125 Gbits/s (2.5 Gbits/s data rate), with a full-
duplex synchronous interface with built-in clock and
data recovery (CDR), along with up to 400k usable
FPGA system gates. The CDR circuitry is a macro-
cell available from Agere's smart silicon macro
library, and has already been implemented in numer-
ous applications including ASICs, standard products,
and FPSCs to create interfaces for SONET/SDH,
STS-48/STM-16, STS-192/STM-64, and 10 Gbit
Ethernet applications. With the addition of protocol
and access logic such as protocol-independent fram-
ers, asynchronous transfer mode (ATM) framers,
packet-over-SONET (POS) interfaces, and framers
for HDLC for Internet protocol (IP), designers can
build a configurable interface retaining proven back-
plane driver/receiver technology. Designers can also
use the device to drive high-speed data transfer
across buses within a system that are not SONET/
SDH based. For example, designers can build a 20
Gbits/s bridge for 10 Gbits/s Ethernet; the high-
speed SERDES interfaces can comprise two XAUI
interfaces with configurable back-end interfaces such
as XGMII or POS-PHY4. The ORT82G5 can also be
used to provide a full 10 Gbits/s backplane data con-
nection with protection between a line card and
switch fabric.
The ORT82G5 offers a clockless high-speed inter-
face for interdevice communication on a board or
across a backplane. The built-in clock recovery of the
ORT82G5 allows for higher system performance,
easier-to-design clock domains in a multiboard sys-
tem, and fewer signals on the backplane. Network
designers will benefit from the backplane transceiver
as a network termination device.The first version of
the device supports 8b/10b encoding/decoding and
link state machines for Ethernet, fibre-channel, and
InfiniBand™. Version II adds SONET data scram-
bling/descrambling, streamlined SONET framing,
transport overhead handling, plus the programmable
logic to terminate the network into proprietary sys-
tems. For non-SONET applications, all SONET func-
tionality is hidden from the user and no prior
networking knowledge is required.
Version II adds decimation and interpolation for con-
nections at 622 Mbits/s rates.
Table 1. ORCA ORT82G5 Family—Available FPGA Logic
Device
ORT82G5
PFU
Rows
36
PFU
Columns
36
Total
PFUs
1296
User I/O
372/432 ‡
LUTs
10,368
EBR
Blocks
12
EBR Bits Usable†
(k) Gates (k)
111 380—800
† The embedded core and interface are not included in the above gate counts. The usable gate counts range from a logic-only gate count
to a gate count assuming that 20% of the PFUs/SLICs are being used as RAMs. The logic-only gate count includes each PFU/SLIC
(counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of
the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output logic, CLK, and I/O buffers). PFUs used as RAM are
counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. Embedded block RAM
(EBR) is counted as four gates per bit plus each block has an additional 25k gates. 7k gates are used for each PLL and 50k gates for the
embedded system bus and microprocessor interface logic. Both the EBR and PLLs are conservatively utilized in the gate count calcula-
tions.
‡ 372 user I/Os out of a total of 432 user I/Os are bonded in the 680 PBGAM package.
1 page  
Preliminary Data Sheet
July 2001
ORCA ORT82G5 FPSC Eight-Channel
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Programmable Features
s High-performance programmable logic:
— 0.13 µm 7-level metal technology.
— Internal performance of >250 MHz.
— Over 400k usable system gates.
— Meets multiple I/O interface standards.
— 1.5 V operation (30% less power than 1.8 V oper-
ation) translates to greater performance.
s Traditional I/O selections:
— LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V) I/Os.
— Per pin-selectable I/O clamping diodes provide
3.3 V PCI compliance.
— Individually programmable drive capability:
24 mA sink/12 mA source, 12 mA sink/6 mA
source, or 6 mA sink/3 mA source.
— Two slew rates supported (fast and slew-limited).
— Fast-capture input latch and input flip-flop
(FF)/latch for reduced input setup time and zero
hold time.
— Fast open-drain drive capability.
— Capability to register 3-state enable signal.
— Off-chip clock drive capability.
— Two-input function generator in output path.
s New programmable high-speed I/O:
— Single-ended: GTL, GTL+, PECL, SSTL3/2
(class I and II), HSTL (Class I, III, IV), ZBT, and
DDR.
— Double-ended: LVDS, bused-LVDS, and LVPECL.
Programmable, parallel termination (100 Ω) is
also supported for these I/Os.
— Customer defined: ability to substitute arbitrary
standard cell I/O to meet fast-moving standards.
s New capability to (de)multiplex I/O signals:
— New DDR on both input and output at rates up to
311 MHz (622 MHz effective rate).
— New 2x and 4x downlink and uplink capability per
I/O (i.e., 50 MHz internal to 200 MHz I/O).
s Enhanced twin-quad programmable function unit
(PFU):
— Eight 16-bit look-up tables (LUTs) per PFU.
— Nine user registers per PFU, one following each
LUT, and organized to allow two nibbles to act
independently, plus one extra for arithmetic opera-
tions.
— New register control in each PFU has two inde-
pendent programmable clocks, clock enables,
local set/reset, and data selects.
— New LUT structure allows flexible combinations of
LUT4, LUT5, new LUT6, 4 → 1 MUX, new
8 → 1 MUX, and ripple mode arithmetic functions
in the same PFU.
— 32 x 4 RAM per PFU, configurable as single- or
dual-port. Create large, fast RAM/ROM blocks
(128 x 8 in only eight PFUs) using the SLIC
decoders as bank drivers.
— Soft-wired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU
through fast internal routing which reduces rout-
ing congestion and improves speed.
— Flexible fast access to PFU inputs from routing.
— Fast-carry logic and routing to all four adjacent
PFUs for nibble-wide, byte-wide, or longer arith-
metic functions, with the option to register the
PFU carry-out.
s Abundant high-speed buffered and nonbuffered rout-
ing resources provide 2x average speed improve-
ments over previous architectures.
s Hierarchical routing optimized for both local and glo-
bal routing with dedicated routing resources. This
results in faster routing times with predictable and
efficient performance.
s SLIC provides eight 3-statable buffers, up to a 10-bit
decoder, and PAL™-like and-or-invert (AOI) in each
programmable logic cell.
s New 200 MHz embedded quad-port RAM blocks,
2 read ports, 2 write ports, and 2 sets of byte lane
enables. Each embedded RAM block can be config-
ured as:
— 1—512 x 18 (quad-port, two read/two write) with
optional built in arbitration.
— 1—256 x 36 (dual-port, one read/one write).
— 1—1k x 9 (dual-port, one read/one write).
— 2—512 x 9 (dual-port, one read/one write for
each).
— 2 RAMS with arbitrary number of words whose
sum is 512 or less by 18 (dual-port, one read/one
write).
— Supports joining of RAM blocks.
— Two 16 x 8-bit content addressable memory
(CAM) support.
— FIFO 512 x 18, 256 x 36, 1k x 9, or dual 512 x 9.
— Constant multiply (8 x 16 or 16 x 8).
— Dual variable multiply (8 x 8).
s Embedded 32-bit internal system bus plus 4-bit par-
ity interconnects FPGA logic, microprocessor inter-
face (MPI), embedded RAM blocks, and embedded
standard cell blocks with 66 MHz bus performance.
Included are built-in system registers that act as the
control and status center for the device.
Agere Systems Inc.
5
5 Page 
Preliminary Data Sheet
July 2001
ORCA ORT82G5 FPSC Eight-Channel
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
System-Level Features (continued)
Configuration
The FPGAs functionality is determined by internal con-
figuration RAM. The FPGAs internal initialization/con-
figuration circuitry loads the configuration data at
powerup or under system control. The configuration
data can reside externally in an EEPROM or any other
storage media. Serial EEPROMs provide a simple, low
pin-count method for configuring FPGAs.
The RAM is loaded by using one of several configura-
tion modes. Supporting the traditional master/slave
serial, master/slave parallel, and asynchronous periph-
eral modes, the Series 4 also utilizes its microproces-
sor interface and embedded system bus to perform
both programming and readback. Daisy chaining of
multiple devices and partial reconfiguration are also
permitted.
Other configuration options include the initialization of
the embedded-block RAM memories and FPSC mem-
ory as well as system bus options and bit stream error
checking. Programming and readback through the
JTAG (IEEE 1149.2) port is also available meeting in-
system programming (ISP) standards (IEEE 1532
Draft).
Additional Information
Contact your local Agere representative for additional
information regarding the ORCA Series 4 FPGA
devices, or visit our website at:
http://www.agere.com/orca
ORT82G5 Overview
Device Layout
The ORT82G5 is a backplane transceiver FPSC with
embedded CDR and SERDES circuitry and 8b/10b
encoding/decoding. It is intended for high-speed serial
backplane data transmission. Built using Series 4
reconfigurable system-on-chips (SoC) architecture, it
also contains up to 400k usable FPGA system gates.
The ORT82G5 contains an FPGA base array, an eight-
channel clock and data recovery macro, and an eight-
channel 8b/10b interface on a single monolithic chip.
version II of this device, which will be plug-in compati-
ble to version I, also adds SONET scrambling capabil-
ity. The version II features are not described in this data
sheet. Figure 1 shows the ORT82G5 block diagram.
Boundary scan for the ORT82G5 only includes pro-
grammable I/Os and does not include any of the
embedded block I/Os.
Backplane Transceiver Interface
The ORT82G5 backplane transceiver FPSC has eight
channels, each operating at up to 3.125 Gbits/s
(2.5 Gbits/s data rate) with a full-duplex synchronous
interface with built-in clock recovery (CDR). The CDR
macro with 8b/10b provides guaranteed ones density
for the CDR, byte alignment, and error detection.
The CDR interface provides a physical medium for
high-speed asynchronous serial data transfer between
system devices. Devices can be on the same PC-
board, on separate boards connected across a back-
plane, or connected by cables. This core is intended
for, but not limited to, terminal equipment in SONET/
SDH, Gbit Ethernet, 10 Gbit Ethernet, ATM, fibre-chan-
nel, and Infiniband systems.
The SERDES circuitry consists of receiver, transmitter,
and auxiliary functional blocks. The receiver accepts
high-speed (up to 3.125 Gbits/s) serial data. Based on
data transitions the receiver locks an analog receive
PLL for each channel to retime the data, then demulti-
plexes down to parallel bytes and clock. The transmitter
operates in the reverse direction. Parallel bytes are
multiplexed up to 3.125 Gbits/s serial data for off-chip
communication. The transmitter generates the neces-
sary 3.125 GHz clocks for operation from a lower
speed reference clock.
This device will support 8b/10b encoding/decoding,
which is capable of frame synchronization and physical
link monitoring. Figure 2 shows the internal architec-
ture of the ORT82G5 backplane transceiver core.
Agere Systems Inc.
11
11 Page | ||
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| PDF Descargar | [ Datasheet ORT82G5.PDF ] | |
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