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ORT4622 Schematic ( PDF Datasheet ) - Agere Systems

Teilenummer ORT4622
Beschreibung Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
Hersteller Agere Systems
Logo Agere Systems Logo 




Gesamt 30 Seiten
ORT4622 Datasheet, Funktion
Preliminary Data Sheet
March 2000
ORCA® ORT4622 Field-Programmable System Chip (FPSC)
Four-Channel x 622 Mbits/s Backplane Transceiver
Introduction
Lucent Technologies Microelectronics Group has
developed a solution for designers who need the
many advantages of FPGA-based design implemen-
tation, coupled with high-speed serial backplane data
transfer. The 622 Mbits/s backplane transceiver
offers a clockless, high-speed interface for interde-
vice communication on a board or across a back-
plane. The built-in clock recovery of the ORT4622
allows for higher system performance, easier-to-
design clock domains in a multiboard system, and
fewer signals on the backplane. Network designers
will benefit from the backplane transceiver as a net-
work termination device. The backplane transceiver
offers SONET scrambling/descrambling of data and
streamlined SONET framing, pointer moving, and
transport overhead handling, plus the programmable
logic to terminate the network into proprietary sys-
tems. For non-SONET applications, all SONET func-
tionality is hidden from the user and no prior
networking knowledge is required.
Embedded Core Features
s Implemented in an ORCA Series 3 FPGA array.
s Allows wide range of applications for SONET net-
work termination application as well as generic data
moving for high-speed backplane data transfer.
s No knowledge of SONET/SDH needed in generic
applications. Simply supply data, 78 MHz clock, and
a frame pulse.
s High-speed interface (HSI) function for clock/data
recovery serial backplane data transfer without
external clocks.
Table 1. ORCA ORT4622—Available FPGA Logic
s HSI function uses Lucent Technologies Microelec-
tronics Group’s proven 622 Mbits/s serial interface
core.
s Four-channel HSI function provides 622 Mbits/s
serial interface per channel for a total chip band-
width of 2.5 Gbits/s (full duplex).
s LVDS I/Os compliant with EIA*-644, support hot
insertion.
s 8:1 data multiplexing/demultiplexing for 77.76 MHz
byte-wide data processing in FPGA logic.
s On-chip phase-lock loop (PLL) clock meets B jitter
tolerance specification of ITU-T Recommendation
G.958 (0.6 UIP-P at 250 kHz).
s Powerdown option of HSI receiver on a per-
channel basis.
s Highly efficient implementation with only 3% over-
head vs. 25% for 8B10B coding.
s In-Band management and configuration.
s Streamlined pointer processor (pointer mover) for
8 kHz frame alignment to system clocks.
s Built-in boundry scan (IEEE1149.1 JTAG).
s FIFOs align incoming data across all four channels
for STS-48 (2.5 Gbits/s) operation (in quad STS-12
format).
s 1 + 1 protection supports STS-12/STS-48 redun-
dancy by either software or hardware control for
protection switching applications.
* EIA is a registered trademark of Electronic Industries Associa-
tion.
IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Device
ORT4622
Usable
System
Gates
60K—120K
Number of
LUTs
4032
Number of
Registers
5304
Max User
RAM
64K
Max User
I/Os
Array Size
Number of
PFUs
259 18 x 28 504
‡ The embedded core and interface are not included in the above gate counts. The usable gate count range from a logic-only gate count to
a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as
108 gates per PFU/SLIC), including 12 gates pre-LUT/FF pair (eight per PFU), and 12 gates per SLC/FF pair (one per PFU). Each of the
four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are
counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU.






ORT4622 Datasheet, Funktion
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
Description (continued)
Timing and simulation output files from ORCA Foundry
are also compatible with many third-party analysis
tools. Its bit stream generator is then used to generate
the configuration data which is loaded into the FPSC’s
internal configuration RAM.
When using the bit stream generator, the user selects
options that affect the functionality of the FPSC. Com-
bined with the front-end tools, ORCA Foundry pro-
duces configuration data that implements the various
logic and routing options discussed in this data sheet.
FPSC Design Kit
Development is facilitated by an FPSC design kit
which, together with ORCA Foundry and third-party
synthesis and simulation engines, provides all software
and documentation required to design and verify an
FPSC implementation. Included in the kit are the FPSC
configuration manager, HDL gate-level structural
netlists, all necessary synthesis libraries, and complete
online documentation. The kit's software couples with
ORCA Foundry, providing a seamless FPSC design
environment. More information can be obtained by vis-
iting the ORCA website or contacting a local sales
office, both listed on the last page of this document.
FPGA Logic Overview
ORCA Series 3 FPGA logic is a new generation of
SRAM-based FPGA logic built on the successful
Series 2 FPGA line from Lucent Technologies Micro-
electronics Group, with enhancements and innovations
geared toward today’s high-speed designs on a single
chip. Designed from the start to be synthesis friendly
and to reduce place and route times while maintaining
the complete routability of the ORCA Series 2 devices,
the Series 3 more than doubles the logic available in
each logic block and incorporates system-level features
that can further reduce logic requirements and
increase system speed. ORCA Series 3 devices con-
tain many new patented enhancements and are offered
in a variety of packages, speed grades, and tempera-
ture ranges.
ORCA Series 3 FPGA logic consists of three basic ele-
ments: programmable logic cells (PLCs), programma-
ble input/output cells (PICs), and system-level features.
An array of PLCs is surrounded by PICs. Each PLC
contains a programmable function unit (PFU), a sup-
plemental logic and interconnect cell (SLIC), local rout-
ing resources, and configuration RAM. Most of the
FPGA logic is performed in the PFU, but decoders,
PAL-like functions, and 3-state buffering can be per-
formed in the SLIC. The PICs provide device inputs
and outputs and can be used to register signals and to
perform input demultiplexing, output multiplexing, and
other functions on two output signals. Some of the sys-
tem-level functions include the new microprocessor
interface (MPI) and the programmable clock manager
(PCM).
PLC Logic
Each PFU within a PLC contains eight 4-input (16-bit)
look-up tables (LUTs), eight latches/flip-flops (FFs),
and one additional flip-flop that may be used indepen-
dently or with arithmetic functions.
The PFU is organized in a twin-quad fashion: two sets
of four LUTs and FFs that can be controlled indepen-
dently. LUTs may also be combined for use in arith-
metic functions using fast-carry chain logic in either
4-bit or 8-bit modes. The carry-out of either mode may
be registered in the ninth FF for pipelining. Each PFU
may also be configured as a synchronous 32 x 4
single- or dual-port RAM or ROM. The FFs (or latches)
may obtain input from LUT outputs or directly from
invertible PFU inputs, or they can be tied high or tied
low. The FFs also have programmable clock polarity,
clock enables, and local set/reset.
The SLIC is connected to PLC routing resources and to
the outputs of the PFU. It contains 3-state, bidirectional
buffers and logic to perform up to a 10-bit AND function
for decoding, or an AND-OR with optional INVERT
(AOI) to perform PAL-like functions. The 3-state drivers
in the SLIC and their direct connections to the PFU out-
puts make fast, true 3-state buses possible within the
FPGA logic, reducing required routing and allowing for
real-world system performance.
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ORT4622 pdf, datenblatt
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
ORT4622 Overview (continued)
FPSC Configuration
Configuration of the ORT4622 occurs in two stages,
FPGA bit stream configuration and embedded core
setup.
FPGA Configuration
Prior to becoming operational, the FPGA goes through
a sequence of states, including powerup initialization,
configuration, start-up, and operation. The FPGA logic
is configured by standard FPGA bit stream configura-
tion means as discussed in the Series 3 FPGA data
sheet. Additionally, for the ORT4622, the location of the
CPU interface to the embedded core, either on the
device pins or at the FPGA/embedded core boundary,
is configured via FPGA configuration and is defined via
the ORT4622 design kit. The default configuration sets
the CPU interface pins to be active. A simple micropro-
cessor emulation soft Intellectual Property (IP) core
that uses very small FPGA logic is available from
Lucent. This microprocessor core sets up the embed-
ded core via a state machine and allows the ORT4622
to work in an independent system without an external
microprocessor interface.
Embedded Core Setup
The embedded core operation is set up via the embed-
ded core CPU interface. All options for the operation of
the core are configured according to the device register
map presented in the detailed description section of
this data sheet.
During the powerup sequence, the ORT4622 device
(FPGA programmable circuit and the core) is held in
reset. All the LVDS output buffers and other output
buffers are held in 3-state. All flip-flops in core area are
in reset state, with the exception of the boundry scan
shift registers, which can only be reset by Boundary
Scan Reset. After powerup reset, the FPGA can start
configuration. During FPGA configuration, the
ORT4622 core will be held in reset and all the local bus
interface signals are forced high, but the following
active-high signals (PROT_SWITCH_A,
PROT_SWITCH_C, TX_TOH_CK_EN, SYS_FP,
LINE_FP) are forced low. The CORE_READY signal
sent from the embedded core to FPGA is held low, indi-
cating core is not ready to interact with FPGA logic. At
the end of the FPGA configuration sequence, the
CORE_READY signal will be held low for six SYS_CLK
cycles after DONE, TRI_IO and RST_N (core global
reset) are high. Then it will go active-high, indicating
the embedded core is ready to function and interact
with FPGA programmable circuit. During FPGA recon-
figuration when DONE and TRI_IO are low, the
CORE_READY signal sent from the core to FPGA will
be held low again to indicate the embedded core is not
ready to interact with FPGA logic. During FPGA partial
configuration, CORE_READY stays active. The same
FPGA configuration sequence described previously will
repeat again.
The initialization of the embedded core consists of two
steps: register configuration and synchronization of the
alignment FIFO. In order to configure the embedded
core, the registers need to be unlocked by writing 0xA0
to address 0x04 and writing 0x01 to address 0x05.
Control registers 0x04 and 0x05 are lock registers. If
the output bus of the data, serial TOH port, and TOH
clock and TOH frame pulse are controlled by 3-state
registers (the use of the registers for 3-state output
control is optional; these output 3-state enable signals
are brought across the local bus interface and available
to the FPGA side), the next step is to activate the 3-
state output bus and signals by taking them to func-
tional state from high-impedance state. This can be
done by writing 0x01 to correspond bits of the channel
registers 0x20, 0x38, 0x50, and 0x68. If the 3-state
control is done in FPGA logic or external logic instead
of in the embedded core registers, this step should be
done in that particular control logic also.
In addition, the synchronization of selected streams is
recommended for some networking systems applica-
tions. This is a resync of the alignment FIFO after the
enabled channels have a valid frame pulse. Here are
the procedures: Put all of the streams to be aligned,
including disabled streams, into their required align-
ment mode. Force AIS-L in all streams to be synchro-
nized (refer to register map, write 0x01 to DB1 of
register 0x20, 0x38, 0x50, 0x68). Wait four frames.
Write a 0x01 to the FIFO alignment resync register, bit
DB1 of register 0x06. Wait four frames. Release the
AIS-L in all streams (write 1 to DB1 of register 0x20,
0x38, 0x50, 0x68). This procedures allows normal data
flow through the embedded core.
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