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PDF ORLI10G Data sheet ( Hoja de datos )
| Número de pieza | ORLI10G | |
| Descripción | Quad 2.5 Gbits/s 10 Gbits/s / and 12.5 Gbits/s Line Interface FPSC | |
| Fabricantes | Agere Systems | |
| Logotipo |  |
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Data Sheet
October 2001
ORCA® ORLI10G Quad 2.5 Gbits/s
10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Introduction
Agere Systems Inc. has developed a new ORCA
Series 4 based FPSC which combines a high-speed
line interface with a flexible FPGA logic core. Built on
the Series 4 reconfigurable embedded system-on-
chips (SoC) architecture, the ORLI10G consists of an
OIF standard (OIF 99.102.5) compliant XSBI or
OIF-SFI4-01.0 SFI-4, 10 Gbits/s or 12.5 Gbits/s
transmit and 10 Gbits/s or 12.5 Gbits/s receive line
interface. Both transmit and receive interfaces con-
sist of 16-bit LVDS data up to 850 Mbits/s, integrated
transmit and receive programmable PLLs for data
rate conversions between the line-side and system-
side data rates, and a programmable logic interface
at the system end for use with SONET/SDH, Ether-
net, or OTN/digital wrapper with strong FEC system
device data standards. In addition to the embedded
functionality, the device will include up to 400k of
usable FPGA gates. The line interface includes logic
to divide the data rate down to 212 MHz or less
(1/4 line rate) or 106 MHz or less (1/8 line rate) for
transfer to the FPGA logic. The ORLI10G is designed
to connect directly to Agere’s 10 Gbits/s TTRN0110G
MUX and TRCV0110G deMUX or Agere’s
12.5 Gbits/s TTRN0126 MUX and TRCV01126
deMUX on the line side, as well as other industry-
standard devices. The programmable logic interface
on the system side allows for direct connection to a
10 Gbits/s Ethernet MAC, a 10 Gbits/s SONET/SDH
framer/data engine, or a 10 Gbits/s/12.5 Gbits/s digi-
tal wrapper/FEC framer/data engine.
For 10 Gbits/s Ethernet, the ORLI10G supports the
physical coding sublayer (PCS), interfaces to the
physical media attachment (PMA), and connects to
the system interface (host or switch) for the proposed
IEEE ® 802.3ae 10 Gbits/s serial LAN PHY.
The ORLI10G FPSC is a high-speed programmable
device for 10G/s data solutions. It can be used as the
interface between the line interface and the system
interface in a variety of emerging networks, including
10 Gbits/s SONET/SDH (OC-192/STM-48),
10 Gbits/s optical transport networks (OTN) using
digital wrapper and strong FEC, or 10 Gbits/s Ether-
net. Other functions include use in Quad OC-48/
STM-16 SONET/SDH systems, interfaces between
Quad OC-48/STM-16 and OC-192/STM-64 compo-
nents, and use as a generic data transfer mechanism
between two devices at 10 Gbits/s rates. Data is
received at the line interface and then sent to either a
4-bit or 8-bit serial-to-parallel converter. On the trans-
mit interface, either a 4-bit or 8-bit parallel-to-serial
converter is used. Thus, the data rate at the internal
FPGA interface is either 1/4 or 1/8 the line rate.
The programmable PLLs on the ORLI10G provide for
great flexibility in handling clock rate conversion due
to differing amounts of overhead bits in various sys-
tem data standards. For example, the ORLI10G can
divide down the STS-192/STM-64 SONET/SDH data
line rate of 622 MHz by 4 to synchronize with a
155 MHz system clock, or the 12.5 Gbits/s Super-
FEC data line rate of 781 MHz can be divided by 8 to
98 MHz system clock or by 8 x 4/5 to provide a
78 MHz system data rate.
Table 1. ORCA ORLI10G—Available FPGA Logic
Device
ORLI10G
PFU
Rows
36
PFU
Columns
36
Total
PFUs
1296
User I/Os* LUTs
432 10,368
EBR
Blocks
12
EBR Bits
(k)
111
Usable
Gates (k)
380—800
* 192 user I/Os for the 416 PBGAM package and 316 user I/Os for the 680 PBGAM package are available out of the 432 possible user
I/Os.
Note: The embedded core and interface are not included in the above gate counts. The usable gate counts range from a logic-only gate
count to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC
(counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU).
Each of the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output logic, CLK, and I/O buffers). PFUs used
as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. Embedded
block RAM (EBR) is counted as four gates per bit, plus each block has an additional 25k gates. 7k gates are used for each PLL and
50k gates for the embedded system bus and microprocessor interface logic. Both the EBR and PLLs are conservatively utilized in
the gate count calculations.
1 page  
Data Sheet
October 2001
ORCA ORLI10G Quad 2.5 Gbits/s
10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Programmable Features (continued)
s Enhanced twin-quad programmable function unit
(PFU):
— Eight 16-bit look-up tables (LUTs) per PFU.
— Nine user registers per PFU, one following each
LUT, and organized to allow two nibbles to act
independently, plus one extra for arithmetic opera-
tions.
— New register control in each PFU has two inde-
pendent programmable clocks, clock enables,
local set/reset, and data selects.
— New LUT structure allows flexible combinations of
LUT4, LUT5, new LUT6, 4 → 1 MUX, new
8 → 1 MUX, and ripple mode arithmetic functions
in the same PFU.
— 32 x 4 RAM per PFU, configurable as single- or
dual-port. Create large, fast RAM/ROM blocks
(128 x 8 in only eight PFUs) using the SLIC
decoders as bank drivers.
— Soft-wired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU
through fast internal routing which reduces routing
congestion and improves speed.
— Flexible fast access to PFU inputs from routing.
— Fast-carry logic and routing to all four adjacent
PFUs for nibble-wide, byte-wide, or longer arith-
metic functions, with the option to register the PFU
carry-out.
s Abundant high-speed buffered and nonbuffered
routing resources provide 2x average speed
improvements over previous architectures.
s Hierarchical routing optimized for both local and
global routing with dedicated routing resources. This
results in faster routing times with predictable and
efficient performance.
s SLIC provides eight 3-stable buffers, up to a 10-bit
decoder, and PAL™-like and-or-invert (AOI) in each
programmable logic cell.
s New 200 MHz embedded quad-port RAM blocks,
two read ports, two write ports, and two sets of byte
lane enables. Each embedded RAM block can be
configured as:
— 1—512 x 18 (quad-port, two read/two write) with
optional built-in arbitration.
— 1—256 x 36 (dual-port, one read/one write).
— 1—1k x 9 (dual-port, one read/one write).
— 2—512 x 9 (dual-port, one read/one write for
each).
— 2 RAMs with arbitrary number of words whose
sum is 512 or less by 18 (dual-port, one read/one
write).
— Supports joining of RAM blocks.
— Two 16 x 8-bit content addressable memory
(CAM) support.
— FIFO 512 x 18, 256 x 36, 1k x 9, or dual 512 x 9.
— Constant multiply (8 x 16 or 16 x 8).
— Dual variable multiply (8 x 8).
s Embedded 32-bit internal system bus plus 4-bit
parity interconnects FPGA logic, microprocessor
interface (MPI), embedded RAM blocks, and
embedded standard cell blocks with 100 MHz bus
performance. Included are built-in system registers
that act as the control and status center for the
device.
s Built-in testability:
— Full boundary scan (IEEE 1149.1 and draft 1149.2
JTAG) for the programmable I/Os only.
— Programming and readback through boundary-
scan port compliant to IEEE Draft 1532:D1.7.
— TS_ALL testability function to 3-state all I/O pins.
— New temperature-sensing diode.
s Improved built-in clock management with
programmable phase-locked loops (PPLLs) provides
optimum clock modification and conditioning for
phase, frequency, and duty cycle from 20 MHz up to
420 MHz. Multiplication of input frequency up to 64x
and division of input frequency down to 1/64x
possible.
s New cycle stealing capability allows a typical 15% to
40% internal speed improvement after final place
and route. This feature also enables compliance with
many setup/hold and clock to out I/O specifications
and may provide reduced ground bounce for output
buses by allowing flexible delays of switching output
buffers.
Agere Systems Inc.
5
5 Page 
Data Sheet
October 2001
ORCA ORLI10G Quad 2.5 Gbits/s
10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
System-Level Features (continued)
Configuration
The FPGAs functionality is determined by internal con-
figuration RAM. The FPGAs internal initialization/con-
figuration circuitry loads the configuration data at
powerup or under system control. The configuration
data can reside externally in an EEPROM or any other
storage media. Serial EEPROMs provide a simple, low
pin-count method for configuring FPGAs.
The RAM is loaded by using one of several configura-
tion modes. Supporting the traditional master/slave
serial, master/slave parallel, and asynchronous periph-
eral modes, the Series 4 also utilizes its microproces-
sor interface and embedded system bus to perform
both programming and readback. Daisy chaining of
multiple devices and partial reconfiguration are also
permitted.
Other configuration options include the initialization of
the embedded-block RAM memories and FPSC
memory as well as system bus options and bit stream
error checking. Programming and readback through
the JTAG (IEEE 1149.2) port is also available meeting
in-system programming (ISP) standards (IEEE 1532
Draft).
Additional Information
Contact your local Agere representative for additional
information regarding the ORCA Series 4 FPGA
devices, or visit our website at:
http://www.agere.com/orca
ORLI10G Overview
Device Layout
The ORLI10G FPSC provides a high-speed transmit
and receive line interface combined with FPGA logic.
The device is based on the 1.5 V OR4E4 FPGA. The
ORLI10G consists of an embedded backplane trans-
ceiver core and a full OR4E4 36x36 FPGA array.
The ORLI10G is a line interface device that contains an
FPGA base array, a 10 Gbits/s line interface block, and
programmable PLLs to do the overhead clock rate con-
versions on a single monolithic chip. The embedded
portion includes:
s Line Interface: This consists of a 16-bit LVDS receive
data bus and a 16-bit LVDS transmit bus operating
up to 850 Mbits/s per input/output pair. Each 4-bit
LVDS
I/O has a high-speed LVDS clock (operating up to
850 MHz) associated with it.
s MUX/deMUX: This performs the MUXing and
deMUXing between the high-speed line interface
data operating at the line rate and system data oper-
ating at 1/4 or 1/8 the line rate.
s On-board PLLs: This is used to align system-side
data with the line-side data, which is at a slightly
higher data bandwidth than the system data because
of the addition of overhead due to encoding.
Figure 1 shows the ORLI10G block diagram.
10G Mode
The ORLI10G can operate in one of two data modes:
10G mode or Quad 2.5G mode.
In 10G (or single-channel) mode, all 16 LVDS transmit
data outputs are assumed to be one data bus with one
LVDS clock provided off chip for the data. Likewise, all
16 LVDS receive data inputs are assumed to be one
data bus with one LVDS input clock provided for the
data.
Transmit Path
In 10G mode, the transmit data from the FPGA logic is
passed to the embedded core as a single 128- or 64-bit
bus. An off-chip transmit reference clock is divided
down in the core by 8 (for 128-bit to 16-bit MUX) or by
4 (for 64-bit to 16-bit MUX). All four transmit clock out-
puts are therefore synchronized.
Agere Systems Inc.
11
11 Page | ||
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| PDF Descargar | [ Datasheet ORLI10G.PDF ] | |
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