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PDF OCX160 Data sheet ( Hoja de datos )
| Número de pieza | OCX160 | |
| Descripción | OCX160 Crosspoint Switch | |
| Fabricantes | ETC | |
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OCX160 Crosspoint Switch
Preliminary Data Sheet
Features
• 667 Mb/s port data bandwidth, >50Gb/s aggregate bandwidth • Full Broadcast and multicast capability
• Low power CMOS, 2.5V and 3.3V power supply
• SRAM-based, in-system programmable
• 160 configurable I/O ports
– 80 dedicated differential input ports
– 80 dedicated differential output ports
– Supports LVDS and LVPECL I/O
– LVTTL control interface
– Output Enable control for all outputs
• Non-blocking switch matrix
– Patented ActiveArray™ matrix for superior performance
– Double-buffered configuration RAM cells for simultaneous
global updates
– One-to-One and One-to-Many connections
– Special broadcast mode routes one input to
all outputs at maximum data rate
• Registered and flow-through data modes
– 333 MHz synchronous mode
– 667 Mb/s asynchronous mode
– Low jitter and signal skew
– Low duty cycle distortion
• RapidConfigure™ parallel interface for
configuration and readback
• JTAG serial interface for configuration and
Boundary Scan testing
– ImpliedDisconnect™ function for single cycle disconnect/ • 420 BGA package with 1.27mm ball spacing
connect
Description
The OCX™ family of SRAM-based devices are non-blocking n X n digital crosspoint switches capable of data
rates of 667 Megabits per second per port. The I/O ports are fixed as either input or output ports. The input ports
support flow-through mode only. The output ports are individually programmable to operate in either flow-
through (asynchronous) or registered (synchronous) mode. Each output register may be clocked by a global
clock or a next neighbor clock source.
The patented ActiveArray provides greater density, superior performance, and greater flexibility compared to a
traditional n:1 multiplexer architecture. The OCX devices support various operating modes covering one input to
one output at a time as well as one input to many outputs, plus a special broadcast mode to program one input to
all outputs while maintaining maximum data rates. In all modes data integrity and connections are maintained on
all unchanged data paths.
The RapidConfigure parallel interface allows fast configuration of both the Output Buffers and the switch
matrix. Readback is supported for device test and verification purposes. The OCX160 also supports the industry
standard JTAG (IEEE 1149.1) interface for boundary scan testing. The JTAG interface can also be used to
download configuration data to the device and readback data. A functional block diagram of the OCX160 is
shown in Figure 1.
Applications
• SONET/SDH and DWDM
• Digital Cross-Connects
• System Backplanes and Interconnects
• High Speed Test Equipment
• ATM Switch Cores
• Video Switching
160
IN[79:0]
Input
Buffers
80 x 80
Crosspoint
Switch Matrix
Output
Buffers
160
OUT[79:0]
2 CLK
OE#
RapidConfigure
Signals
RCA[6:0] 7
RCB[6:0] 7
RCI[3:0] 4
RCO[4:0] 5
RC_CLK#
RC_EN#
UPDATE#
Configuration and
Programming Logic
TCK
TMS
TDI
TRST#
TDO
JTAG
Signals
HW_RST#
Figure 1 OCX160 Functional Block Diagram
I-Cube, Inc.
[Rev. 1.6] 2/20/01
1
1 page  
OCX160 Crosspoint Switch—Preliminary Data Sheet
Figures
Figure 1
Figure 2
Figure 3
Figure 4
OCX160 Functional Block Diagram .................................................................................................... 1
OCX160 Switch Matrix ........................................................................................................................ 7
Input and Output Buffer Configuration ................................................................................................ 8
Next Neighbor Clock Block Diagram ................................................................................................ 10
Figure 5 OCX160 JTAG Architecture .............................................................................................................. 15
Figure 6
Figure 7
Figure 8
Figure 9
OCX160 JTAG State Machine ........................................................................................................... 16
Transmitting LVDS Signal Circuit ..................................................................................................... 22
Receiving LVDS Signal Circuit ......................................................................................................... 22
Transmitting LVPECL Signal Circuit ................................................................................................ 23
Figure 10 Receiving LVPECL Signal Circuit..................................................................................................... 23
Figure 11 Registered Output Mode Timing ........................................................................................................ 28
Figure 12
Figure 13
Figure 14
Figure 15
Flow-Through Mode Timing .............................................................................................................. 28
Output Enable Timing ........................................................................................................................ 28
Duty Cycle Distortion ......................................................................................................................... 29
RapidConfigure Write Cycle .............................................................................................................. 29
Figure 16 RapidConfigure Read Cycle ............................................................................................................... 30
Figure 17 JTAG Timing ...................................................................................................................................... 30
Figure 18
Figure 19
Figure 20
Figure 21
Typical Performance LVDS mode ..................................................................................................... 31
Typical Performance LVPECL mode................................................................................................. 31
OCX160 Package Pinout .................................................................................................................... 32
OCX160 Package—Bottom, Top and Side Views ............................................................................. 38
Figure 22 Power Consumption Diagram for the OCX160 using LVDS............................................................. 40
Figure 23 Power Consumption Diagram for the OCX160 using LVPECL........................................................ 41
I-Cube, Inc.
[Rev. 1.6] 2/20/01
5
5 Page 
OCX160 Crosspoint Switch—Preliminary Data Sheet
1.3 RapidConfigure Interface
RapidConfigure (RC) is a 25 signal parallel interface that is used to program the OCX160 device. The 25
pins are allocated as follows:
RCA[6:0] = RapidConfigure Address A. RCA are input pins.
RCB[6:0] = RapidConfigure Address B. RCB are input pins.
RCI[3:0] = RapidConfigure Instruction Bits
RCO[4:0] = RapidConfigure Readback. RCO are output pins.
RC_CLK# = RapidConfigure Clock (negative edge clock)
RC_EN# = RapidConfigure Cycle Enable (active low)
1.3.1 RapidConfigure Programming Instructions
The RC interface supports both write and read types of operations:
1. Write Operations (reset crosspoint and Input or Output Buffer (IOB), configure an
Output Buffer, connect/disconnect crosspoint)
2. Read Operations (Output Buffer and crosspoint configuration read).
Table 3 RapidConfigure Programming Instructions
RCI[3:0]
0000
0001
0010
RCA[6:0]
X
RCB[6:0]
X
0011
X Input Port
Address
0100
Output Port
Address
Data
0101
Cycle 1 Output Port Intput Port
Address
Address
RCO[4:0]
X
Instruction
Description
Reserved
Reserved
Reset Crosspoint
Array
Reset the entire crosspoint array to no
connect. All Output Buffers remain
unchanged by this operation.
Set Array to Broadcast
mode
Connects the input selected by RCB[6:0]
to all output ports and disconnects all
other inputs. The Global Update
(UPDATE#) pin must be held high
during Broadcast mode. Activating the
Global Update pin returns the array to
the previous program condition.
Configure an Output Program an Output Buffer specified by
Buffer
RCA[6:0].
See Table 5 for RCB[6:0] bit assignment
and buffer functionality.
Readback Crosspoint, This is a two-cycle instruction.
Output Buffer status
Specify the crosspoint connect status at
input location specified by RCA[6:0] to
the output location specified by
RCB[6:0].
I-Cube, Inc.
[Rev. 1.6] 2/20/01
11
11 Page | ||
| Páginas | Total 44 Páginas | |
| PDF Descargar | [ Datasheet OCX160.PDF ] | |
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