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NWK933CG Schematic ( PDF Datasheet ) - Mitel Networks

Teilenummer NWK933CG
Beschreibung 3.3V 10/100 Fast Ethernet Transceiver to MII
Hersteller Mitel Networks
Logo Mitel Networks Logo 




Gesamt 18 Seiten
NWK933CG Datasheet, Funktion
NWK933
NWK933
3.3V 10/100 Fast Ethernet Transceiver to MII
Features
q Integrated 10/100 Mbps Ethernet in a Single Chip
Solution
q Single 3.3V Power Supply
q Half Duplex and Full Duplex in both 10BASE-T
and 100BASE-TX
q Full MII for a Glueless MAC Connection
q Extended Register Set
q Integrated 10BASE-T Transceivers and Receive /
Transmit Filters
q Integrated Adaptive Equaliser and Base Line
Wander Correction (for FDDI Killer Packet)
q Full Auto-Negotiation Support for 10BASE-T and
100BASE-TX both Half and Full Duplex
q Link Status Change Interrupt
q Parallel Detection for Supporting Non Auto
Negotiation in Legacy Link Partners
q Low Dynamic Current
q Deep Sleep Low Power Mode <1mA
q Internal Power on Reset
q 64 pin 1mm thick TQFP Package
q Single Magnetics for 10BASE-T and 100BASE-TX
Operation for a Single RJ45 Connector
q Support for Flow Control 802.3 Specification
q Integrated 6 LED Driver
DS5029
Issue no 2.1
Odering Information
NWK933/CG/TP1N
May 1999
q Low External Component Count
q Loop-back mode for diagnostics
q Intelligent power management
(auto shutdown, auto wake)
q Low Transmit Jitter
Description
The NWK933 is a single chip 3.3V CMOS physical
layer solution from MII to the magnetics. It is designed
for 10BASE-T and 100BASE-TX Ethernet, based
on the IEEE 802.3 specifications.
The NWK933 is compatible with the Auto Negotiation
section of IEEE 802.3u and provides all the support
needed for the 802.3 Full duplex specification.
Switch or MAC
NWK933
Isolation
Magnetics
RJ45
Figure 1 System block diagram
1






NWK933CG Datasheet, Funktion
NWK933
Low-Power Mode
This function is set via the management interface.
Using MDC and MDIO, Bit 11 of register 0 is written
high to put the NWK933 into Low-Power mode. The
type of low power mode is dependant on bits 14 and
15 in register 24.
For 24[15:14] = 0:0 the 10BASE-T and 100BASE-TX
transceivers are disabled. The oscillator continues
to run. Both RX_CLK and TX_CLK are stopped, the
RXD bus is held low and TXD, TXEN, and TXER are
ignored. MDC and MDIO are still active for new
commands. This mode is intended to conserve power
when the network connection is not required and the
TXOP/TXON output is undriven. Typical current
consumption is less than 10mA.
For 24[15:14] = 0:1, everything is turned off, including
the voltage references and the oscillator. This mode
must be exited via the management interface. Typical
current consumption is 0.5mA.
For 24[15:14] = 1:0, the only function available is the
signal detect. The NWK933 will detect a signal
amplitude on the cable and activate the interrupt.
MINT can be selected as either an active low or high
interrupt. Typical current consumption is less than
10mA.
For 24[15:14] = 1:1, the NWK933 will automatically
power down into a sleep mode if no activity is seen
on the cable for approx 2 seconds. Power up is also
automatic if activity is seen. Typical current
consumption is less than 10mA.
Loopback Mode
Diagnostic loopback may be selected at any time by
asserting setting Bit 14 in register 0. In 10BASE-T
mode transmission to the TXOP/ TXON output will
be stopped and the RX10 Clock Recovery will receive
input from the TX10 transmit path rather than from
the RXIP/RXIN inputs. In 100BASE-TX mode
transmission to the TXOP/TXON output will be stopped
and the RX100 Clock Recovery will receive input
from the TX100 transmit path.
Repeater Mode
The NWK933 can be put into Repeater Mode by
setting register 24 bit 0 high. In this mode, the CRS
will be active on receive only. In 100Mbps repeater
mode, the NWK933 is able to perform a disconnect
function from the MII. This function is enabled by bit
1 in register 24. (Note that if the device is not in
repeater mode, this bit has no effect). The NWK933
will disconnect from the MII if it receives two
6
consecutive false CRS events with no good frame in
between them or if a false CRS event is longer then
480 +/- 4BT. If the NWK933 receives a good carrier
event (480 +/- 4BT) or a good idle event (idle symbols
for a period of 25000 to 30000 bit time) it will resume
frame transfer to the MII.
A false CRS event happens if, at the beginning of a
carrier event, the JK symbols are not received
correctly.
When the NWK933 is in 100M mode it will count all
false CRS events in register 27 bits 7:0. This counter
is self cleared upon read. If a disconnect event
occurs between the consecutive reads of register 27,
bit 15 in the register will set high.
Auto-Negotiation Enable (ANEN)
Auto-negotiation may be hardware disabled by setting
the ANEN pin to logic zero. During operation, auto-
negotiation can be disabled by setting the ANEN pin
low or by setting bit 12 of register 0 to zero. If auto-
neg is disabled, the NWK933 will lose the link, and
link will be re-established only after the NWK933
control state machine has determined the speed
using bits 13 and 8 of register 0 to determine speed
and duplex respectively.
MII Management Interface, MDC and MDIO
The management interface is a 2 wire serial interface
connecting a PHY to a management entity. The
management unit controls the PHY and gathers
information on the status of the PHY. It does this via
the implemented registers using MDC to clock the
data on the MDIO pin.
Link Status Change Interrupt, MINT
MINT is, by default, an active low interrupt which is
activated whenever a change in the link status occurs.
It can be changed to be active high by setting bit 13
in register 24. The interrupt will remain active until
the controller acknowledges the interrupt by writing
to register 21 (any data). Should one or more link
status changes occur between the assertion of MINT
and an ackowledge, then MINT will be deasserted
and then reasserted (deassertion time between 100ns
and 150ns). Only a single interrupt event may be
queued at any one time. Multiple status changes
between an ackowledge will generate only a single
queued interrupt.

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NWK933CG pdf, datenblatt
NWK933
reg 21 - MII interrupt control register
Bit
21.15:0
Bit name Description
Clear Interrupt Write any data pattern to clear MINT
reg 22, 23 - Test registers
Bit Bit name Description
15:0 reserved test mode only
Default
0
R/W
WO
Default
0000
R/W
res
reg 24- NWK933 specific register
Bit
24.15:14
24.13
24.12
24.11
24.10
24. 9
24.8
24.7
24.6
24.5
24.4
24.3
24.2
24.1
24:0
Bit name
PWRCON[1:0]
MINTPOL
Pol Dis
SQE disable
JAB disable
loop 10
Force RX
Force TX
CRS_CTL
MF
Byp ALIGN
Byp ENC
Byp SCR
DISCEN
RPTR
Description
Default
Low power controls:
00 = full receive path active. No transmit.
01 = Deep sleep (all off including VREF & OSC)
10 = Sleep (generate MII interrupt on activity)
11 = auto shut down, auto wake on activity
00
1 = MINT output active high
0 = MINT output active low
0
1 = disable 10Base-T autopolarity correction
0
1 = disable SQE in 10Base-T half duplex mode
0
0 = in case of jabber the 10Base-T will cut the
transmitted frame (normal operation)
1 = Jabber function disable
0
1 = enable MII loopback in 10Base-T half duplex mode 0
Force receive regardless of link
0
Force transmit regardless of link
0
CRS behavior in full duplex mode:-
0 = CRS is active for transmit only
1= CRS active for receive or transmit
0
1 = MDIO data accepted without preamble
0
0 = normal operation
1 = bypass the aligner function
0
0 = normal operation
1 = bypass the 4B5B encoder function
0
0 = normal operation
1 = bypass the scrambler function
0
0 = disable disconnection events
1 = enable disconnect on false carrier detection
Set repeater mode (affects CRS generation)
0
0
R/W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
12

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