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N82510 Schematic ( PDF Datasheet ) - InnovASIC Inc

Teilenummer N82510
Beschreibung ASYNCHRONOUS SERIAL CONTROLLER
Hersteller InnovASIC Inc
Logo InnovASIC  Inc Logo 




Gesamt 14 Seiten
N82510 Datasheet, Funktion
IA82510
ASYNCHRONOUS SERIAL CONTROLLER
Data Sheet
As of Production Ver. 01
FEATURES
Form, Fit, and Function Compatible with the Intel® 82510
Packaging options available: 28 Pin Plastic or Ceramic DIP, 28 Pin Plastic
Leaded Chip Carrier, 28 Pin Ceramic Leadless Chip Carrier
Asynchronous Serial Channel Operation
Separate Transmit and Receive FIFOs with Programmable Threshold
Programmable Baud Rate Generators up to 288K Baud
Special Protocol Features
- Control Character Recognition
- Auto Echo and Loopback Modes
- 9-Bit Protocol Support
- 5 to 9 Bit Character Format
The IA82510 is a "plug-and-play" drop-in replacement for the original IC. innovASIC produces replacement ICs
using its MILESTM, or Managed IC Lifetime Extension System, cloning technology. This technology produces
replacement ICs far more complex than "emulation" while ensuring they are compatible with the original IC.
MILESTM captures the design of a clone so it can be produced even as silicon technology advances. MILESTM
also verifies the clone against the original IC so that even the "undocumented features" are duplicated. This data
sheet documents all necessary engineering information about the IA82510 including functional and I/O
descriptions, electrical characteristics, and applicable timing.
Package Pinout
D4
D5
D6
D7
INT
TXD
VSS
X2 or OUT2n
X1 or CLK
SCLK or RIn
DSRn or TA or OUT0n
DCDn or ICLK or OUT1n
RXD
CTSn
IA82510
(1) (28)
(2) 28 Pin DIP (27)
(3) (26)
(4) (25)
(5) (24)
(6) (23)
(7) (22)
(8) (21)
(9) (20)
(10) (19)
(11) (18)
(12) (17)
(13) (16)
(14) (15)
D3
D2
D1
D0
A2
A1
A0
VDD
RDn
WRn
CSn
INT
TXD
VSS
X2 or OUT2n
X1 or CLK
SCLK or RIn
DSRn or TA or OUT0n
RESET
RTSn
DTRn or TB
D7 D6 D5 D4 D3 D2 D1
(4) (3) (2) (1) (28) (27) (26)
(5)
(6)
(7) IA82510
(8)
28 Pin LCC
(9)
(10)
(11)
(25)
(24)
(23)
(22)
(21)
(20)
(19)
(12) (13) (14) (15) (16) (17) (18)
D0
A2
A1
A0
VDD
RDn
WRn
Copyright © 2001
innovASIC
The End of Obsolescence
ENG211001219-01
Page 1 of 14
www.innovasic.com
Customer Support:
1-888-824-4184






N82510 Datasheet, Funktion
IA82510
ASYNCHRONOUS SERIAL CONTROLLER
DC Characteristics
Data Sheet
As of Production Ver. 01
Symbol
VIL
VIH1
VIH2
VOL
VOH
ILI
ILO
ICC
IPU
ISTBY
IOHR
IOLR
CIN
CIO
CXTAL
Parameter
Input Low Voltage
Input High Voltage-Cerdip
Input High Voltage-LCC
Output Low Voltage
Output High Voltage
Input Leakage Current
3-State Leakage Current
Power Supply Current
Strapping Pullup Resistor
Standby Supply Current
RTSn, DTRn Strapping Current
RTSn, DTRn Strapping Current
Input Capacitance
I/O Capacitance
X1, X2 Load
Notes
(1)
(1)
(2)
(2),(8)
(3),(8)
(4)
(5)
(6)
(12)
(9)
(10)
(11)
(7)
(7)
Min Max Unit
-0.5 0.7 V
2.1
VDD+.07
V
2.1
VDD+.07
V
0.4 V
2.4 V
±1 µA
±1 µA
1.12 mA/MHz
-283 -137 µA
100 µA
1.92 mA
N/A mA
5 pF
6 pF
6 pF
Notes:
1. Does not apply to CLK/X1 pin, when configured as crystal oscillator input (X1).
2. @IOL = 1.92 mA
3. @IOH = 1.92 mA
4. 0< VIN <VCC
5. 0.4V < VOUT < VCC – 0.4V
6. VDD = 5.5V, VIL = 0.7V (max), VIH = VDD – 0.7V (min), Typ. Val = 1.12 mA/MHz (Not
Tested), Ext. 1X CLK, IOL = IOH = 0
7. Freq. = 1 MHz
8. Does not apply to OUT2/X2 pin, when configured as crystal oscillator output (X2).
9. Freq. = 1 MHz, but input clock not running. Static IDD current is exclusive of input/output
drive requirements and is measured with the clocks stopped and all inputs tied to VDD or
VSS, configured to draw minimum current.
10. Applies only during hardware reset for clock configuration options. Strapping current for
logic HIGH.
11. Applies only during hardware reset for clock configuration options. Strapping current for
logic LOW.
12. Inputs (RTSn, DTRn, TB) with Pullups tested @ Vin = 0.0V, VDD = 5.5V
Copyright © 2001
innovASIC
The End of Obsolescence
ENG211001219-01
Page 6 of 14
www.innovasic.com
Customer Support:
1-888-824-4184

6 Page









N82510 pdf, datenblatt
IA82510
ASYNCHRONOUS SERIAL CONTROLLER
Data Sheet
As of Production Ver. 01
can be altered to the point of confusing the downstream receiver.
Workaround: Change firmware to Manual TX mode to control RTS vs. start of character.
Copyright © 2001
innovASIC
The End of Obsolescence
ENG211001219-01
Page 12 of 14
www.innovasic.com
Customer Support:
1-888-824-4184

12 Page





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