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N80C31BH Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer N80C31BH
Beschreibung CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 16 Seiten
N80C31BH Datasheet, Funktion
80C31BH 80C51BH 87C51
MCS 51
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Automotive
Y Extended Automotive Temperature
Range (b40 C to a125 C Ambient)
Y High Performance CHMOS Process
Y Power Control Modes
Y 4 Kbyte On-Chip ROM EPROM
Y 128 x 8-bit RAM
Y 32 Programmable I O Lines
Y Two 16-Bit Timer Counters
Y 5 Interrupt Sources
Y Quick-Pulse EPROM Programming
Y 2-Level Program Memory Lock EPROM
Y Boolean Processor
Y Programmable Serial Port
Y TTL- and CMOS-Compatible Logic
Levels
Y 64K External Program Memory Space
Y 64K External Data Memory Space
Y IDLE and POWER DOWN Modes
Y ONCE Mode Facilitates System Testing
Y Available in 12 MHz and 16 MHz
Versions
Y Available in PLCC and DIP Packages
(See Packaging Specification Order 231369)
The MCS 51 CHMOS microcontroller products are fabricated on Intel’s reliable CHMOS process and are
functionally compatible with the standard MCS 51 HMOS microcontroller products This technology combines
the high speed and density characteristics of HMOS with the low power attributes of CHMOS This combina-
tion expands the effectiveness of the powerful MCS 51 microcontroller architecture and instruction set
Like the MCS 51 HMOS microcontroller versions the MCS 51 CHMOS microcontroller products have the
following features 4 Kbytes of EPROM ROM (87C51 80C51BH respectively) 128 bytes of RAM 32 I O lines
two 16-bit timer counters a five-source two-level interrupt structure a full duplex serial port and on-chip
oscillator and clock circuitry In addition the MCS 51 CHMOS microcontroller products exhibit low operating
power along with two software selectable modes of reduced activity for further power reduction Idle and
Power Down
The Idle mode freezes the CPU while allowing the RAM timer counters serial port and interrupt system to
continue functioning The Power Down mode saves the RAM contents but freezes the oscillator causing all
other chip functions to be inoperative
The 87C51 is the EPROM version of the 80C51BH It contains 4 Kbytes of on-chip program memory that can
be electrically programmed and can be erased by exposure to ultraviolet light The 87C51 EPROM array uses
a modified Quick-Pulse Programming algorithm by which the entire 4 Kbyte array can be programmed in about
12 seconds
NOTICE
This datasheet contains information on products in full production Specifications within this datasheet
are subject to change without notice Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
January 1995
Order Number 270419-007






N80C31BH Datasheet, Funktion
AUTOMOTIVE 80C31BH 80C51BH 87C51
Mode
Idle
Idle
Power Down
Power Down
Table 2 Status of the External Pins During Idle and Power Down
Program
Memory
ALE
PSEN
PORT0
PORT1
PORT2
Internal
1
1
Data
Data
Data
External
1
1
Float
Data
Address
Internal
0
0
Data
Data
Data
External
0
0
Float
Data
Data
PORT3
Data
Data
Data
Data
NOTE
For more detailed information on the reduced power modes refer to current Embedded Applications Handbook and Applica-
tion Note AP-252 ‘‘Designing with the 80C51BH ’’
internal RAM in this event but access to the port
pins is not inhibited To eliminate the possibility of an
unexpected write to a port pin when Idle is terminat-
ed by reset the instruction following the one that
invokes Idle should not be one that writes to a port
pin or to external memory
POWER DOWN MODE
In the Power Down mode the oscillator is stopped
and the instruction that invokes Power Down is the
last instruction executed The on-chip RAM and
Special Function Registers retain their values until
the Power Down mode is terminated
The only exit from Power Down is a hardware reset
Reset redefines the SFRs but does not change the
on-chip RAM The reset should not be activated be-
fore VCC is restored to its normal operating level and
must be held active long enough to allow the oscilla-
tor to restart and stabilize
DESIGN CONSIDERATIONS
 At power on the voltage on VCC and RST must
come up at the same time for a proper start-up
 Before entering the Power Down mode the con-
tents of the Carry Bit and B 7 must be equal
 When the Idle mode is terminated by a hardware
reset the device normally resumes program exe-
cution from where it left off up to two machine
cycles before the internal reset algorithm takes
control On-chip hardware inhibits access to inter-
nal RAM in this event but access to the port pins
in not inhibited To eliminate the possibility of an
unexpected write when Idle is terminated by re-
set the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory
 An external oscillator may encounter as much as
a 100 pF load at XTAL1 when it starts up This is
due to interaction between the amplifier and its
feedback capacitance Once the external signal
meets the VIL and VIH specifications the capaci-
tance will not exceed 20 pF
 For EPROM versions exposure to light when the
device is in operation may cause logic errors For
this reason it is suggested that an opaque label
be placed over the window when the die is ex-
posed to ambient light
6

6 Page









N80C31BH pdf, datenblatt
AUTOMOTIVE 80C31BH 80C51BH 87C51
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min Max Units
1 TCLCL Oscillator Frequency 3 5 12 MHz
3 5 16
TCHCX
TCLCX
TCLCH
TCHCL
High Time
Low Time
Rise Time
Fall Time
20
20
20
20
ns
ns
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
270419 – 17
SERIAL PORT TIMING SHIFT REGISTER MODE
Symbol
Parameter
TXLXL
TQVXH
TXHQX
TXHDX
TXHDV
Serial Port Clock Cycle Time
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
12 MHz
Oscillator
Min Max
10
700
50
0
700
Variable
Oscillator
Units
Min Max
12TCLCL
10TCLCLb133
2TCLCLb117
0
ms
ns
ns
ns
10TCLCLb133 ns
SHIFT REGISTER MODE TIMING WAVEFORMS
AC TESTING INPUT OUTPUT WAVEFORMS
FLOAT WAVEFORMS
270419 – 15
270419 – 16
AC inputs during testing are driven at VCC b 0 5 for a Logic ‘‘1’’
and 0 45V for a Logic ‘‘0 ’’ Timing measurements are made at VIH
min for a Logic ‘‘1’’ and VIL max for a Logic ‘‘0’’
270419 – 18
For timing purposes a port pin is no longer floating when a 100
mV change from load voltage occurs and begins to float when a
100 mV change from the loaded VOH VOL level occurs IOL IOH
t g20 mA
12

12 Page





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