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PDF N80960SA-16 Data sheet ( Hoja de datos )
| Número de pieza | N80960SA-16 | |
| Descripción | EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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80960SA
EMBEDDED 32-BIT MICROPROCESSOR
WITH 16-BIT BURST DATA BUS
s High-Performance Embedded
Architecture
— 20 MIPS* Burst Execution at 20 MHz
— 7.5 MIPS Sustained Execution
at 20 MHz
s 512-Byte On-Chip Instruction Cache
— Direct Mapped
— Parallel Load/Decode for Uncached
Instructions
s Multiple Register Sets
— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bit Registers
— Four Local Register Sets Stored
On-Chip
— Register Scoreboarding
s Pin Compatible with 80960SB
s Built-in Interrupt Controller
— 4 Direct Interrupt Pins
— 31 Priority Levels, 256 Vectors
s Easy to Use, High Bandwidth 16-Bit Bus
— 32 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
s 32-Bit Address Space, 4 Gigabytes
s 80-Lead Quad Flat Pack (EIAJ QFP)
— 84-Lead Plastic Leaded Chip Carrier
(PLCC)
s Software Compatible with
80960KA/KB/CA/CF Processors
The 80960SA is a member of Intel’s i960® 32-bit processor family, which is designed especially for low cost
embedded applications. It includes a 512-byte instruction cache and a built-in interrupt controller. The 80960SA
has a large register set, multiple parallel execution units and a 16-bit burst bus. Using advanced RISC
technology, this high performance processor is capable of execution rates in excess of 7.5 million instructions
per second*. The 80960SA is well-suited for a wide range of cost sensitive embedded applications including
non-impact printers, network adapters and I/O controllers.
SIXTEEN
32-BIT GLOBAL
REGISTERS
64- BY 32-BIT
LOCAL
REGISTER
CACHE
32-BIT
INSTRUCTION
EXECUTION
UNIT
INSTRUCTION
FETCH UNIT
512-BYTE
INSTRUCTION
CACHE
INSTRUCTION
DECODER
MICRO-
INSTRUCTION
SEQUENCER
MICRO-
INSTRUCTION
ROM
32-BIT
BUS
CONTROL
LOGIC
32-BIT
ADDRESS
16-BIT
BURST
BUS
Figure 1. The 80960SA Processor’s Highly Parallel Architecture
* Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment
Corporation)
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1993
November 1993
Order Number: 272206-002
1 page  
80960SA
1.0 THE i960® PROCESSOR
The 80960SA is a member of the 32-bit architecture
from Intel known as the i960 processor family. These
microprocessors were especially designed to serve
the needs of embedded applications. The embedded
market includes applications as diverse as industrial
automation, avionics, image processing, graphics
and networking. These types of applications require
high integration, low power consumption, quick
interrupt response times and high performance.
Since time to market is critical, embedded micropro-
cessors need to be easy to use in both hardware and
software designs.
All members of the i960 processor family share a
common core architecture which utilizes RISC
technology so that, except for special functions, the
family members are object-code compatible. Each
new processor in the family adds its own special set
of functions to the core to satisfy the needs of a
specific application or range of applications in the
embedded market.
0000 0000H
FFFF FFFFH
ADDRESS SPACE
ARCHITECTURALLY
DEFINED
DATA STRUCTURES
FETCH
INSTRUCTION
CACHE
INSTRUCTION
STREAM
INSTRUCTION
EXECUTION
PROCESSOR STATE
REGISTERS
INSTRUCTION
POINTER
ARITHMETIC
CONTROLS
PROCESS
CONTROLS
TRACE
CONTROLS
LOAD
STORE
SIXTEEN 32-BIT
g0
GLOBAL REGISTERS g15
SIXTEEN 32-BIT r0
LOCAL REGISTERS r15
FOUR 80-BIT
FLOATING POINT REGISTERS
CONTROL REGISTERS
Figure 2. 80960SA Programming Environment
1
5 Page 
80960SA
The 80960SA provides two hardware breakpoint
registers on-chip which, by using a special
command, can be set to any value. When the
instruction pointer matches either breakpoint register
value, the breakpoint handling routine is automati-
cally called.
The 80960SA also provides software breakpoints
through the use of two instructions: MARK and
FMARK. These can be placed at any point in a
program and cause the processor to halt execution
at that point and call the breakpoint handling routine.
The breakpoint mechanism is easy to use and
provides a powerful debugging tool.
Tracing is available for instructions (single step
execution), calls and returns and branching. Each
trace type may be enabled separately by a special
debug instruction. In each case, the 80960SA
executes the instruction first and then calls a trace
handling routine (usually part of a software debug
monitor). Further program execution is halted until
the routine completes, at which time execution
resumes at the next instruction. The 80960SA’s
tracing mechanisms, implemented completely in
hardware, greatly simplify the task of software test
and debug.
For each of the fault types, there are numerous
subtypes that provide specific information about a
fault. The fault handler can use this specific infor-
mation to respond correctly to the fault.
1.1.11 Built-in Testability
Upon reset, the 80960SA automatically conducts an
exhaustive internal test of its major blocks of logic.
Then, before executing its first instruction, it does a
zero check sum on the first eight words in memory to
ensure that the memory image was programmed
correctly. If a problem is discovered at any point
during the self-test, the 80960SA asserts its FAIL pin
and will not begin program execution. Self test takes
approximately 24,000 cycles to complete.
System manufacturers can use the 80960SA’s self-
test feature during incoming parts inspection. No
special diagnostic programs need to be written. The
test is both thorough and fast. The self-test capability
helps ensure that defective parts are discovered
before systems are shipped and, once in the field,
the self-test makes it easier to distinguish between
problems caused by processor failure and problems
resulting from other causes.
1.1.10 Fault Detection
The 80960SA has an automatic mechanism to
handle faults. Fault types include trace and
arithmetic faults. When the processor detects a fault,
it automatically calls the appropriate fault handling
routine and saves the current instruction pointer and
necessary state information to make efficient
recovery possible. Like interrupt handling routines,
fault handling routines are usually written to meet the
needs of specific applications and are often included
as part of the operating system or kernel.
1.1.12 CHMOS
The 80960SA is fabricated using Intel’s CHMOS IV
(Complementary High Speed Metal Oxide Semicon-
ductor) process. The 80960SA is available at 10 and
16 MHz in the QFP package and at 10, 16 and 20
MHz in the PLCC package.
7
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