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PDF PSD814520MT Data sheet ( Hoja de datos )
| Número de pieza | PSD814520MT | |
| Descripción | Flash In-System Programmable ISP Peripherals For 8-bit MCUs | |
| Fabricantes | ST Microelectronics | |
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PSD813F2/3/4/5, PSD833F2
PSD834F2, PSD853F2, PSD854F2
Flash In-System Programmable
(ISP) Peripherals For 8-bit MCUs
PRELIMINARY DATA
FEATURES SUMMARY
s 5V±10% Single Supply Voltage
s Up to 2Mbit of Primary Flash Memory (8 uniform
sectors, 32K x 8)
s Up to 256Kbit Secondary Flash Memory (4
uniform sectors)
s Up to 256Kbit SRAM
s Over 3,000 Gates of PLD: DPLD and CPLD
s 27 Reconfigurable I/O ports
s Enhanced JTAG Serial Port
s Programmable power management
s High Endurance:
– 100,000 Erase/WRITE Cycles of Flash
Memory
– 1,000 Erase/WRITE Cycles of PLD
Figure 1. 52-pin, Plastic, Quad, Flat Package
PQFP52 (T)
Figure 2. 52-lead, Plastic-Lead Chip Carrier
PLCC52 (K)
June 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Rev. 3.0
1/103
1 page  
PSD8XXF2/3/4/5
POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 28. Power-down Mode’s Effect on Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 29. APD Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 29. PSD8XXFX Timing and Stand-by Current during Power-down Mode. . . . . . . . . . . . . . . 59
Figure 30. Enable Power-down Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 30. Power Management Mode Registers PMMR0 (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 31. Power Management Mode Registers PMMR2 (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . 61
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 32. APD Counter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Reset of Flash Memory Erase and Program Cycles (on the PSD834Fx) . . . . . . . . . . . . . . . . . 63
Figure 31. Reset (RESET) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode . . . . . . . . . . . . . . 64
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 65
Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 34. JTAG Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
JTAG Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Security and Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 35. JTAG Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 32. PLD ICC /Frequency Consumption (5 V range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 33. PLD ICC /Frequency Consumption (3 V range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 36. Example of PSD8XXFX Typical Power Calculation at VCC = 5.0 V (Turbo Mode On) . . 69
Table 37. Example of PSD8XXFX Typical Power Calculation at VCC = 5.0 V (Turbo Mode Off) . . 70
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 38. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5/103
5 Page 
PSD8XXF2/3/4/5
PSD8XXFX ARCHITECTURAL OVERVIEW
PSD8XXFX devices contain several major func-
tional blocks. Figure 3 shows the architecture of
the PSD8XXFX device family. The functions of
each block are described briefly in the following
sections. Many of the blocks perform multiple
functions and are user configurable.
Memory
Each of the memory blocks is briefly discussed in
the following paragraphs. A more detailed discus-
sion can be found in the section entitled “MEMO-
RY BLOCKS“ on page 18.
The 1 Mbit or 2 Mbit (128K x 8, or 256K x 8) Flash
memory is the primary memory of the PSD8XXFX.
It is divided into 8 equally-sized sectors that are in-
dividually selectable.
The optional 256 Kbit (32K x 8) secondary Flash
memory is divided into 4 equally-sized sectors.
Each sector is individually selectable.
The optional SRAM is intended for use as a
scratch-pad memory or as an extension to the
MCU SRAM. If an external battery is connected to
Voltage Stand-by (VSTBY, PC2), data is retained in
the event of power failure.
Each sector of memory can be located in a differ-
ent address space as defined by the user. The ac-
cess times for all memory types includes the
address latching and DPLD decoding time.
Page Register
The 8-bit Page Register expands the address
range of the MCU by up to 256 times. The paged
address can be used as part of the address space
to access external memory and peripherals, or in-
ternal memory and I/O. The Page Register can
also be used to change the address mapping of
sectors of the Flash memories into different mem-
ory spaces for IAP.
PLDs
The device contains two PLDs, the Decode PLD
(DPLD) and the Complex PLD (CPLD), as shown
in Table 2, each optimized for a different function.
The functional partitioning of the PLDs reduces
power consumption, optimizes cost/performance,
and eases design entry.
Table 2. PLD I/O
Name
Inputs
Outputs
Product
Terms
Decode PLD (DPLD) 73
17
42
Complex PLD (CPLD) 73
19
140
The DPLD is used to decode addresses and to
generate Sector Select signals for the PSD8XXFX
internal memory and registers. The DPLD has
combinatorial outputs. The CPLD has 16 Output
Macrocells (OMC) and 3 combinatorial outputs.
The PSD8XXFX also has 24 Input Macrocells
(IMC) that can be configured as inputs to the
PLDs. The PLDs receive their inputs from the PLD
Input Bus and are differentiated by their output
destinations, number of product terms, and mac-
rocells.
The PLDs consume minimal power. The speed
and power consumption of the PLD is controlled
by the Turbo bit in PMMR0 and other bits in the
PMMR2. These registers are set by the MCU at
run-time. There is a slight penalty to PLD propaga-
tion time when invoking the power management
features.
I/O Ports
The PSD8XXFX has 27 individually configurable I/
O pins distributed over the four ports (Port A, B, C,
and D). Each I/O pin can be individually configured
for different functions. Ports can be configured as
standard MCU I/O ports, PLD I/O, or latched ad-
dress outputs for MCUs using multiplexed ad-
dress/data buses.
The JTAG pins can be enabled on Port C for In-
System Programming (ISP).
Ports A and B can also be configured as a data
port for a non-multiplexed bus.
MCU Bus Interface
PSD8XXFX interfaces easily with most 8-bit
MCUs that have either multiplexed or non-multi-
plexed address/data buses. The device is config-
ured to respond to the MCU’s control signals,
which are also used as inputs to the PLDs. For ex-
amples, please see the section entitled “MCU Bus
Interface Examples“ on page 43.
11/103
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet PSD814520MT.PDF ] | |
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