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PS11017 Schematic ( PDF Datasheet ) - Powerex Power

Teilenummer PS11017
Beschreibung FLAT-BASE TYPE INSULATED TYPE
Hersteller Powerex Power
Logo Powerex Power Logo 




Gesamt 6 Seiten
PS11017 Datasheet, Funktion
MITMSUITBSIUSBHISSHEIMSIECMOINCDOUNCDTUOCRTO<RAp<pAlipcpalticoantiSopneScpifeicciIfnicteIlnlitgeellnigtePnotwPeorwMeor dMuoled>ule>
Some parametric limits are subject to change.
PS11PS01117017
FLAFTL-BATA-SBEASTEYPTEYPE
INSIUNLSAUTLEADTETDYPTEYPE
PS11017
INTEGRATED FUNCTIONS AND FEATURES
• 3-phase IGBT inverter bridge configured by the latest 3rd.
generation IGBT and diode technologies.
• Circuit for dynamic braking of motor regenerative energy.
• Inverter output current capability IO (Note 1):
Type Name
100% load
150% over load
PS11017
17.0A (rms)
25.5A (rms), 1min
(Note 1) : The inverter output current is assumed to be sinu-
soidal and the peak current value of each of the
above loading cases is defined as : IOP = IO × √2
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:
• For P-Side IGBTs : Drive circuit, High voltage isolated high-speed level shifting, Short-circuit protection (SC),
Bootstrap circuit supply scheme (Single drive-power-supply) and Under voltage protection (UV).
• For N-Side IGBTs : Drive circuit, Short circuit protection (SC), Control-supply Under voltage and Over voltage protection (OV/UV), Sys-
tem Over-temperature protection (OT), Fault output (FO) signaling circuit, and Current-Limit warning signal output
(CL)
• For Brake circuit IGBT : Drive circuit
• Warning and Fault signaling :
FO1 : Short circuit protection for lower-leg IGBTs and Input interlocking against spurious arm shoot-through.
FO2 : N-side control supply abnormality locking (OV/UV)
FO3 : System over-temperature protection (OT).
CL : Warning for inverter current overload condition
• For system feedback control : Analogue signal feedback reproducing actual inverter phase current (3φ).
• Input Interface : 5V CMOS/TTL compatible, Schmitt trigger input, and Arm-Shoot-Through interlock protection.
APPLICATION
Acoustic noise-less 3.7kW/AC200V class 3 phase inverter and other motor control applica-
tions.
PACKAGE OUTLINES
56 ± 0.8
15.5
1
2 ± 0.3
7
6 ± 0.3
(102)
23
0.5
4-φ5
31
12.7 ± 0.3
63.5 ± 0.8
105 ± 0.5
115 ± 1
96
3
36
17.5
2.5
4-R2
4-φ4.5
MOUNTING
HOLE
20.4 ± 1
4-R5
4-φ3.2
3
17 ± 0.8
Terminals Assignment:
1 CBU+
2 CBU–
3 CBV+
4 CBV–
5 CBW+
6 CBW–
7 GND
8 NC
9 VDH
10 CL
11 FO1
12 FO2
13 FO3
14 CU
15 CV
16 CW
17 UP
18 VP
19 WP
20 UN
21 VN
22 WN
23 Br
31 P
32 Br
33 N
34 U
35 V
36 W
(Fig. 1)
LABEL
May 2001






PS11017 Datasheet, Funktion
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11017
FLAT-BASE TYPE
INSULATED TYPE
Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART
VCIN
V(hold)
off
on
on
off
IC
0
+ICL
(VS)
0
N-side IGBT Current
N-side FWDi Current
Ref
VC
VCL
0
off
on
t(hold)
Delay time
td(read)
–ICL
Fig. 9 START-UP SEQUENCE
Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT
Normally at start-up, Fo and CL output signals will be pulled-up
High to Supply voltage (OFF level); however, FO1 output may fall to
Low (ON) level at the instant of the first ON input pulse to an N-Side
5V
IGBT. This can happen particularly when the boot-strap capacitor is
of large size. FO1 resetting sequence (together with the boot-strap
charging sequence) is explained in the following graph
ASIPM
DC-Bus voltage
VPN 0
Control voltage supply
VDH 0
Boot-strap voltage
N-Side input signal
VDB
0
VCIN(N)
on
PWM starts
a)
CPU
b)
5.1k
R
R
10k
0.1nF 0.1nF
UP,VP,WP,UN,VN,WN,Br
F01,F02,F03,CL
CU,CV,CW
GND(Logic)
P-Side input signal VCIN(P) on
Brake input signal
FO1 output signal
VCIN(Br) on
FOI on
a) Boot-strap charging scheme :
Apply a train of short ON pulses at all N-IGBT input pins for ad-
equate charging (pulse width = approx. 20µs number of pulses =10
~ 500 depending on the boot-strap capacitor size)
b) FO1 resetting sequence:
Apply ON signals to the following input pins : Br Un/Vn/Wn
Up/Vp/Wp in that order.
May 2001

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