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PDF PS11014 Data sheet ( Hoja de datos )
| Número de pieza | PS11014 | |
| Descripción | FLAT-BASE TYPE INSULATED TYPE | |
| Fabricantes | Powerex Power | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PS11014 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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MITMSUITBSIUSBHISSHEIMSIECMOINCDOUNCDTUOCRTO<RAp<pAlipcpalticoantiSopneScpifeicciIfnicteIlnlitgeellnigtePnotwPeorwMeor dMuoled>ule>
PS11PS01114014
FLAFTL-BATA-SBEASTEYPTEYPE
INSIUNLSAUTLEADTETDYPTEYPE
PS11014
INTEGRATED FUNCTIONS AND FEATURES
• Converter bridge for 3 phase AC-to-DC power conversion.
• Circuit for dynamic braking of motor regenerative energy.
• 3-phase IGBT inverter bridge configured by the latest 3rd.
generation IGBT and diode technology.
• Inverter output current capability IO (Note 1):
Type Name
100% load
150% over load
PS11014
5.0A (rms)
7.5A (rms), 1min
(Note 1) : The inverter output current is assumed to be sinu-
soidal and the peak current value of each of the
above loading cases is defined as : IOP = IO × √2
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:
• For inverter side upper-leg IGBTs : Drive circuit, High voltage isolated high-speed level shifting, Short circuit protection (SC).
Bootstrap circuit supply scheme (single drive power supply) and Under voltage protection (UV).
• For inverter side lower-leg IGBTs : Drive circuit, Short circuit protection (SC).
Control supply circuit under- & over- voltage protection (OV/UV).
System over temperature protection (OT). Fault output signaling circuit (FO) and Current limit warn-
ing signal output (CL).
• For Brake circuit IGBT : Drive circuit
• Warning and Fault signaling :
FO1 : Short circuit protection for lower-leg IGBTs and Input interlocking against spurious arm shoot-through.
FO2 : N-side control supply abnormality locking (OV/UV).
FO3 : System over-temperature protection (OT).
CL : Warning for inverter current overload condition
• For system feedback control : Analogue signal feedback reproducing actual inverter output phase currents (3φ).
• Input Interface : 5V CMOS/TTL compatible, Schmitt trigger input, and Arm-Shoot-Through interlock protection.
APPLICATION
Acoustic noise-less 0.75kW/AC200V class 3 phase inverter and other motor control appli-
cations
PACKAGE OUTLINES
4-R2
0.5
1 2 3 4 5 6 7 8 91011121314151617181920212223
24
2424
2 ± 0.3
2-φ4
2-R4
5.08 ± 0.3 ! 9 = 45.72 ± 0.8
31 32 33 34 35 36 37 38 39 40
1.2
(Fig. 1)
LABEL
54 ± 0.5
62 ± 1
V6
Terminals Assignment:
1 CBU+
2 CBU–
3 CBV+
4 CBV–
5 CBW+
6 CBW–
7 GND
8 NC
9 VDH
10 CL
11 FO1
12 FO2
13 FO3
14 CU
15 CV
16 CW
17 UP
18 VP
19 WP
20 UN
21 VN
22 WN
23 Br
31 R
32 S
33 T
34 P1
35 P2
36 N
37 B
38 U
39 V
40 W
V Control Pin top
portion details
0.3
0.5 ± 0.03
V Main terminal top
portion details
0.8
±
0.5
0
0.35MAX
12
±
0.5
0
0.6
Jan . 2000
1 page  
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11014
FLAT-BASE TYPE
INSULATED TYPE
Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING
LINEARITY
5
VC–
4 min max
VC–(200%)
VDH=15V
TC=–20~100˚C
3
VC0
2
VC+(200%)
1
Analogue output signal
data hold range
VC+
0
–400 –300 –200 –100 0 100 200 300 400
Real load current peak value.(%)(Ic=Io! 2)
(Fig. 4)
Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING
“DATA HOLD” DEFINITION
VC
500µs
0V VCH(5µs)
VCH(505µs)
rCH=
VCH(505µs)-VCH(5µs)
VCH(5µs)
Note ; Ringing happens around the point where the signal output
voltage changes state from “analogue” to “data hold” due
to test circuit arrangement and instrumentational trouble.
Therefore, the rate of change is measured at a 5 µs delayed point.
Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART
Input signal VCIN(p) of each phase upper arm 0V
Input signal VCIN(n) of each phase lower arm
Gate signal Vo(p) of each phase upper arm
(ASIPM internal)
0V
0V
Gate signal Vo(n) of each phase upper arm
(ASIPM internal)
0V
Error output FO1 0V
Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta-
neously in “LOW” level.
By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “FO” signal is outputted. After an “input
interlock” operation the circuit is latched. The “FO” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input,
whichever comes in later.
Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION
Input signal VCIN of each phase
upper arm
0V
Short circuit sensing signal VS
Gate signal Vo of each phase
upper arm(ASIPM internal)
0V
0V
Error output FO1 0V
SC delay time
Note : Short circuit protection operation. The protection operates with “FO” flag and reset on a pulse-by-pulse scheme. The protection by
gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”).
Jan . 2000
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet PS11014.PDF ] | |
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