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93LC46B Schematic ( PDF Datasheet ) - Microchip Technology

Teilenummer 93LC46B
Beschreibung 1K Microwire Compatible Serial EEPROM
Hersteller Microchip Technology
Logo Microchip Technology Logo 




Gesamt 30 Seiten
93LC46B Datasheet, Funktion
93AA46A/B/C, 93LC46A/B/C,
93C46A/B/C
1K Microwire Compatible Serial EEPROM
Device Selection Table
Part Number
93AA46A
93AA46B
93LC46A
93LC46B
93C46A
93C46B
93AA46C
93LC46C
93C46C
VCC Range
1.8-5.5
1.8-5-5
2.5-5.5
2.5-5.5
4.5-5.5
4.5-5.5
1.8-5.5
2.5-5.5
4.5-5.5
ORG Pin
No
No
No
No
No
No
Yes
Yes
Yes
Features:
• Low-Power CMOS Technology
• ORG Pin to Select Word Size for ‘46C’ Version
• 128 x 8-bit Organization ‘A’ Devices (no ORG)
• 64 x 16-bit Organization ‘B’ Devices (no ORG)
• Self-Timed Erase/Write Cycles (including
Auto-Erase)
• Automatic Erase All (ERAL) Before Write All
(WRAL)
• Power-On/Off Data Protection Circuitry
• Industry Standard 3-Wire Serial I/O
• Device Status Signal (Ready/Busy)
• Sequential Read Function
• 1,000,000 Erase/Write Cycles
• Data Retention > 200 Years
• Pb-free and RoHS Compliant
• Temperature Ranges Supported:
- Industrial (I) -40°C to +85°C
- Automotive (E) -40°C to +125°C
Word Size Temp Ranges
Packages
8-bit
16-bit
8-bit
16-bit
8-bit
16-bit
8- or 16-bit
8- or 16-bit
8- or 16-bit
I P, SN, ST, MS, OT, MC, MN
I P, SN, ST, MS, OT, MC, MN
I, E P, SN, ST, MS, OT, MC, MN
I, E P, SN, ST, MS, OT, MC, MN
I, E P, SN, ST, MS, OT, MC, MN
I, E P, SN, ST, MS, OT, MC, MN
I P, SN, ST, MS, MC, MN
I, E P, SN, ST, MS, MC, MN
I, E P, SN, ST, MS, MC, MN
Pin Function Table
Name
Function
CS
CLK
DI
DO
VSS
NC
ORG
VCC
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
No internal connection
Memory Configuration
Power Supply
Description:
The Microchip Technology Inc. 93XX46A/B/C devices
are 1Kbit low-voltage serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93AA46C, 93LC46C or 93C46C are dependent
upon external logic levels driving the ORG pin to set
word size. For dedicated 8-bit communication, the
93AA46A, 93LC46A or 93C46A devices are available,
while the 93AA46B, 93LC46B and 93C46B devices
provide dedicated 16-bit communication. Advanced
CMOS technology makes these devices ideal for low-
power, nonvolatile memory applications. The entire
93XX Series is available in standard packages includ-
ing 8-lead PDIP and SOIC, and advanced packaging
including 8-lead MSOP, 6-lead SOT-23, 8-lead
2x3 DFN/TDFN and 8-lead TSSOP. All packages are
Pb-free (Matte Tin) finish.
2002-2011 Microchip Technology Inc.
DS21749J-page 1






93LC46B Datasheet, Funktion
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.0 FUNCTIONAL DESCRIPTION
When the ORG pin (93XX46C) is connected to VCC,
the (x16) organization is selected. When it is connected
to ground, the (x8) organization is selected. Instruc-
tions, addresses and write data are clocked into the DI
pin on the rising edge of the clock (CLK). The DO pin is
normally held in a High-Z state except when reading
data from the device, or when checking the Ready/
Busy status during a programming operation. The
Ready/Busy status can be verified during an erase/
write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. DO will enter the High-Z
state on the falling edge of CS.
2.1 Start Condition
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (Read, Write, Erase, EWEN, EWDS, ERAL
or WRAL). As soon as CS is high, the device is no
longer in Standby mode.
An instruction following a Start condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
Note:
When preparing to transmit an instruction,
either the CLK or DI signal levels must be
at a logic low as CS is toggled active high.
2.2 Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. In order to
limit this current, a resistor should be connected
between DI and DO.
2.3 Data Protection
All modes of operation are inhibited when VCC is below
a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices
or 3.8V for ‘93C’ devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
Note:
For added protection, an EWDS command
should be performed after every write
operation and an external 10 kpull-
down protection resistor should be added
to the CS pin.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before the initial ERASE or WRITE instruction
can be executed.
Block Diagram
VCC VSS
Memory
Array
Address
Decoder
DI
ORG*
CS
Data Register
Mode
Decode
Logic
CLK
Clock
Register
Address
Counter
Output DO
Buffer
*ORG input is not available on A/B devices
DS21749J-page 6
2002-2011 Microchip Technology Inc.

6 Page









93LC46B pdf, datenblatt
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
3.0 PIN DESCRIPTIONS
TABLE 3-1: PIN DESCRIPTIONS
Name
PDIP
SOIC
TSSOP MSOP
DFN(1) TDFN(1)
SOT-23
Rotated
SOIC
Function
CS
11 1 1 1
1
5
3 Chip Select
CLK
22
2
22
2
4
4 Serial Clock
DI
33 3 3 3
3
3
5 Data In
DO
44
4
44
4
1
6 Data Out
Vss
55 5 5 5
5
2
7 Ground
ORG/NC 6
6
6
6
6
6
8 Organization/93XX46C
No Internal Connection/
93XX46A/B
NC 7 7 7 7 7 7 — 1 No Internal Connection
VCC
88
8
88
8
6
2 Power Supply
Note 1: The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating.
3.1 Chip Select (CS)
A high level selects the device; a low level deselects
the device and forces it into Standby mode. However, a
programming cycle that is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into Standby mode as soon as the
programming cycle is completed.
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal
control logic is held in a Reset status.
3.2 Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93XX series
device. Opcodes, address and data bits are clocked in
on the positive edge of CLK. Data bits are also clocked
out on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing opcode, address and data.
CLK is a “don't care” if CS is low (device deselected). If
CS is high, but the Start condition has not been
detected (DI = 0), any number of clock cycles can be
received by the device without changing its status (i.e.,
waiting for a Start condition).
CLK cycles are not required during the self-timed write
(i.e., auto erase/write) cycle.
After detection of a Start condition the specified number
of clock cycles (respectively low-to-high transitions of
CLK) must be provided. These clock cycles are
required to clock in all required opcode, address and
data bits before an instruction is executed. CLK and DI
then become “don't care” inputs waiting for a new Start
condition to be detected.
3.3 Data In (DI)
Data In (DI) is used to clock in a Start bit, opcode,
address and data synchronously with the CLK input.
3.4 Data Out (DO)
Data Out (DO) is used in the Read mode to output data
synchronously with the CLK input (TPD after the
positive edge of CLK).
This pin also provides Ready/Busy status information
during erase and write cycles. Ready/Busy status infor-
mation is available on the DO pin if CS is brought high
after being low for minimum Chip Select low time (TCSL)
and an erase or write operation has been initiated.
The Status signal is not available on DO if CS is held
low during the entire erase or write cycle. In this case,
DO is in the High-Z mode. If status is checked after the
erase/write cycle, the data line will be high to indicate
the device is ready.
Note:
After a programming cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
3.5 Organization (ORG)
When the ORG pin is connected to VCC or Logic HI, the
(x16) memory organization is selected. When the ORG
pin is tied to VSS or Logic LO, the (x8) memory
organization is selected. For proper operation, ORG
must be tied to a valid logic level.
93XX46A devices are always (x8) organization and
93XX46B devices are always (x16) organization.
DS21749J-page 12
2002-2011 Microchip Technology Inc.

12 Page





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