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PDF 93C86 Data sheet ( Hoja de datos )
| Número de pieza | 93C86 | |
| Descripción | 8K/16K 5.0V Microwire Serial EEPROM | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 93C86 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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Not recommended for new designs –
Please use 93LC76C or 93LC86C.
93C76/86
8K/16K 5.0V Microwire Serial EEPROM
Features:
• Single 5.0V supply
• Low-power CMOS technology
- 1 mA active current typical
• ORG pin selectable memory configuration
1024 x 8- or 512 x 16-bit organization (93C76)
2048 x 8- or 1024 x 16-bit organization (93C86)
• Self-timed erase and write cycles
(including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device status signal during erase/write cycles
• Sequential read function
• 1,000,000 erase/write cycles ensured
• Data retention > 200 years
• 8-pin PDIP/SOIC package
• Temperature ranges supported
- Commercial (C):
- Industrial (I):
- Automotive (E)
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Description:
The Microchip Technology Inc. 93C76/86 are 8K and
16K low voltage serial Electrically Erasable PROMs.
The device memory is configured as x8 or x16 bits
depending on the ORG pin setup. Advanced CMOS
technology makes these devices ideal for low power
nonvolatile memory applications. These devices also
have a Program Enable (PE) pin to allow the user to
write protect the entire contents of the memory array.
The 93C76/86 is available in standard 8-pin PDIP and
8-pin surface mount SOIC packages.
Package Types
PDIP Package
CS 1
CLK 2
DI 3
DO 4
SOIC Package
CS 1
CLK 2
DI 3
DO 4
8 VCC
7 PE
6 ORG
5 VSS
8 VCC
7 PE
6 ORG
5 VSS
Block Diagram
VCC VSS
Memory
Array
Data
Register
DI
Mode
PE Decode
CS Logic
Address
Decoder
Address
Counter
Output
Buffer
DO
CLK
Clock
Generator
1996-2012 Microchip Technology Inc.
DS21132F-page 1
1 page  
2.0 PRINCIPLES OF OPERATION
When the ORG pin is connected to VCC, the x16 orga-
nization is selected. When it is connected to ground,
the x8 organization is selected. Instructions, addresses
and write data are clocked into the DI pin on the rising
edge of the clock (CLK). The DO pin is normally held in
a high-Z state except when reading data from the
device, or when checking the Ready/Busy status
during a programming operation. The Ready/Busy
status can be verified during an erase/write operation
by polling the DO pin; DO low indicates that program-
ming is still in progress, while DO high indicates the
device is ready. The DO will enter the high-impedance
state on the falling edge of the CS.
2.1 Start Condition
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device opera-
tion (Read, Write, Erase, EWEN, EWDS, ERAL and
WRAL). As soon as CS is high, the device is no longer
in the Standby mode.
An instruction following a Start condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction are clocked
in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become “don't care” bits until a new Start condition is
detected.
2.2 DI/DO
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin.
93C76/86
2.3 Erase/Write Enable and Disable
(EWEN, EWDS)
The 93C76/86 powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be
preceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or VCC is removed from the device. To protect against
accidental data disturb, the EWDS instruction can be
used to disable all erase/write functions and should
follow all programming operations. Execution of a READ
instruction is independent of both the EWEN and EWDS
instructions.
2.4 Data Protection
During power-up, all programming modes of operation
are inhibited until VCC has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
VCC has fallen below 1.4V.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction can
be executed.
1996-2012 Microchip Technology Inc.
DS21132F-page 5
5 Page 
5.0 PACKAGING INFORMATION
5.1 Package Marking Information
8-Lead PDIP
XXXXXXXX
XXXXXNNN
YYWW
8-Lead SOIC (.150”)
XXXXXXXX
XXXXYYWW
NNN
93C76/86
Example
93C76
017
0410
Example
93C86
/SN0410
017
Legend:
XX...X
Y
YY
WW
NNN
e3
*
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
1996-2012 Microchip Technology Inc.
DS21132F-page 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet 93C86.PDF ] | |
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