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93C56 Schematic ( PDF Datasheet ) - ATMEL Corporation

Teilenummer 93C56
Beschreibung 3-Wire Serial EEPROMs
Hersteller ATMEL Corporation
Logo ATMEL Corporation Logo 




Gesamt 21 Seiten
93C56 Datasheet, Funktion
Features
Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
User-selectable Internal Organization
– 1K: 128 x 8 or 64 x 16
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
Three-wire Serial Interface
2 MHz Clock Rate (5V)
Self-timed Write Cycle (10 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
Automotive Grade, Extended Temperature and Lead-Free/Halogen-Free
Devices Available
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP, 8-lead TSSOP,
and 8-ball dBGA2 Packages
Description
The AT93C46/56/66 provides 1024/2048/4096 bits of serial electrically erasable pro-
grammable read-only memory (EEPROM), organized as 64/128/256 words of 16 bits
each (when the ORG pin is connected to VCC), and 128/256/512 words of 8 bits each
(when the ORG pin is tied to ground). The device is optimized for use in many indus-
trial and commercial applications where low-power and low-voltage operations are
essential. The AT93C46/56/66 is available in space-saving 8-lead PDIP, 8-lead
JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP, 8-lead TSSOP, and 8-lead dBGA2
packages.
The AT93C46/56/66 is enabled through the Chip Select pin (CS) and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the
data is clocked out serially on the DO pin. The Write cycle is completely self-timed,
and no separate Erase cycle is required before Write. The Write cycle is only enabled
when the part is in the Erase/Write Enable state. When CS is brought high following
the initiation of a Write cycle, the DO pin outputs the Ready/Busy status of the part.
The AT93C46/56/66 is available in 2.7V to 5.5V and 1.8V to 5.5V versions.
Table 1. Pin Configurations
Pin Name
Function
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
GND
Ground
VCC
Power Supply
ORG
Internal Organization
DC Don’t Connect
8-lead SOIC
8-lead dBGA2
CS 1
SK 2
DI 3
DO 4
8 VCC
7 DC
6 ORG
5 GND
VCC
DC
ORG
GND
8
7
6
5
1 CS
2 SK
3 D1
4 D0
8-lead PDIP
CS 1
SK 2
DI 3
DO 4
8 VCC
7 DC
6 ORG
5 GND
8-lead SOIC
Rotated (R)
(1K JEDEC Only)
DC
VCC
CS
SK
1
2
3
4
8 ORG
7 GND
6 DO
5 DI
8-lead MAP
VCC 8
DC 7
ORG 6
GND 5
1 CS
2 SK
3 DI
4 DO
8-lead TSSOP
CS 1
SK 2
DI 3
DO 4
8 VCC
7 DC
6 ORG
5 GND
Three-wire
Serial
EEPROMs
1K (128 x 8 or 64 x 16)
2K (256 x 8 or 128 x 16)
4K (512 x 8 or 256 x 16)
AT93C46
AT93C56(1)
AT93C66(2)
Note: 1. This device is not recom-
mended for new designs.
Please refer to AT93C56A.
2. This device is not recom-
mended for new designs.
Please refer to AT93C66A.
0172Z–SEEPR–9/05
1






93C56 Datasheet, Funktion
Functional
Description
The AT93C46/56/66 is accessed via a simple and versatile three-wire serial communi-
cation interface. Device operation is controlled by seven instructions issued by the host
processor. A valid instruction starts with a rising edge of CS and consists of a start bit
(logic “1”) followed by the appropriate op code and the desired memory address
location.
READ (READ): The Read (READ) instruction contains the address code for the mem-
ory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string.
ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes
into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write
Enable (EWEN) instruction must be executed first before any programming instructions
can be carried out. Please note that once in the EWEN state, programming remains
enabled until an EWDS instruction is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
Erase instruction and address are decoded. The DO pin outputs the Ready/Busy status
of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A
logic “1” at pin DO indicates that the selected memory location has been erased and the
part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be
written into the specified memory location. The self-timed programming cycle tWP starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
Read/Busy status of the part if CS is brought high after being kept low for a minimum of
250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1”
indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
Ready/Busy status cannot be obtained if the CS is brought high after the end of the self-
timed programming cycle tWP.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-
ory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy
status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).
The WRAL instruction is valid only at VCC = 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the Read instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
6 AT93C46/56/66
0172Z–SEEPR–9/05

6 Page









93C56 pdf, datenblatt
AT93C56(1) Ordering Information
Ordering Code(2)
Package
Operation Range
AT93C56-10PI-2.7
AT93C56-10SI-2.7
AT93C56W-10SI-2.7
AT93C56-10TI-2.7
AT93C56Y1-10YI-2.7
8P3
8S1
Industrial
8S2
(40°C to 85°C)
8A2
8Y1
AT93C56-10PI-1.8
AT93C56-10SI-1.8
AT93C56W-10SI-1.8
AT93C56-10TI-1.8
AT93C56Y1-10YI-1.8
8P3
8S1
Industrial
8S2
(40°C to 85°C)
8A2
8Y1
Notes: 1. This device is not recommended for new designs. Please refer to AT93C56A.
2. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in Table 3 on page 3 and Table 4 on
page 4.
Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
Options
2.7 Low Voltage (2.7V to 5.5V)
1.8 Low Voltage (1.8V to 5.5V)
12 AT93C46/56/66
0172Z–SEEPR–9/05

12 Page





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