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NS32FX16-15 Schematic ( PDF Datasheet ) - National

Teilenummer NS32FX16-15
Beschreibung Imaging/Signal Processor
Hersteller National
Logo National Logo 




Gesamt 30 Seiten
NS32FX16-15 Datasheet, Funktion
PRELIMINARY
July 1991
NS32FX16-15 NS32FX16-20 NS32FX16-25
Imaging Signal Processor
General Description
The NS32FX16 is a high-performance 32-bit member of the
Series 32000 EPTM family of National’s Embedded System
ProcessorsTM specifically optimized for CCITT Group 2 and
Group 3 Facsimile Applications Data Modems Voice Mail
Systems Laser Printers or any combination of the above
It can perform all the computations and control functions
required for a stand-alone Fax system a PC add-in Fax
Data Modem card or a Laser Fax system
It also meets the performance requirements to implement
9600 and 7200 bps modems complying with CCITT V 29
and V 27 standards
The NS32FX16 provides a 16 Mbyte Linear external ad-
dress space and a 16-bit external data bus
The CPU core which is the same as that of the NS32CG16
incorporates a 32-bit ALU and instruction pipeline and an
8-byte prefetch queue
Also integrated on-chip with the CPU are a DSP Module and
a 384-byte RAM Array The DSP Module executes vector
operations on complex variables and is specially designed
to enhance performance in modem applications The vector
operations can also be used to efficiently implement FIR
Filters and other DSP primitives The on-chip RAM Array is
used to store the coefficients of the various filters and can
be accessed by both the CPU and the DSP Module
The NS32FX16 capabilities can be expanded by using an
external floating point unit (FPU) which directly interfaces to
the NS32FX16 using the slave protocol The CPU-FPU clus-
ter features high speed execution of the floating-point in-
structions
The NS32FX16 highly-efficient architecture combined with
the NS32CG16 graphics instructions and the high-perform-
ance vector operation capability makes the device the ideal
choice for PostscriptTM and Fax applications
Features
Y Software compatible with the Series 32000 EP
processors
Y Designed around the CPU core of the NS32CG16
Y 32-bit architecture and implementation
Y On-chip DSP Module for high-speed DSP operations
Y Special support for graphics applications
18 graphics instructions
Binary compression expansion capability for font
storage using RLL encoding
Pattern magnification
Interface to an external BITBLT processing units for
fast color BITBLT operations
Y 384-byte on-chip RAM array
Y On-chip clock generator
Y Floating-point support via the NS32081 or NS32181
Y Optimal interface to large memory arrays via the
NS32CG821 and the DP84xx family of DRAM control-
lers
Y Power save mode
Y High-speed CMOS technology
Y 68-pin PLCC package
Block Diagram
Series 32000 is a registered trademark of National Semiconductor Corporation
EPTM and Embedded System ProcessorsTM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL EE10818
TL EE 10818 – 67
RRD-B30M115 Printed in U S A






NS32FX16-15 Datasheet, Funktion
1 0 Product Introduction
The NS32FX16 is a high speed CMOS microprocessor in
the Series 32000 EP family
It includes two main execution units the NS32CG16 com-
patible CPU core and the DSP Module The CPU core is
designed for general purpose computations and system
control functions The DSP Module is tuned to perform the
DSP primitives needed in Voice Band Modems The
NS32FX16 also incorporates a 384-byte RAM Array as a
shared resource for both the CPU core and the DSP Mod-
ule
The NS32FX16 is software-compatible with all other CPUs
in the family
The device incorporates all of the Series 32000 advanced
architectural features with the exception of the virtual mem-
ory capability
Brief descriptions of the NS32FX16 features that are shared
with other members of the family are provided below
Powerful Addressing Modes Nine addressing modes
available to all instructions are included to access data
structures efficiently
Data Types The architecture provides for numerous data
types such as byte word doubleword and BCD which may
be arranged into a wide variety of data structures
Symmetric Instruction Set While avoiding special case
instructions that compilers can’t use the Series 32000 fami-
ly incorporates powerful instructions for control operations
such as array indexing and external procedure calls which
save considerable space and time for compiled code
Memory-to-Memory Operations The Series 32000 CPUs
represent two-address machines This means that each op-
erand can be referenced by any one of the addressing
modes provided
This powerful memory-to-memory architecture permits
memory locations to be treated as registers for all useful
operations This is important for temporary operands as well
as for context switching
Large Uniform Addressing The NS32FX16 has 24-bit ad-
dress pointers that can address up to 16 megabytes without
any segmentation this addressing scheme provides flexible
memory management without add-on expense
Modular Software Support Any software package for the
Series 32000 architecture can be developed independent of
all other packages without regard to individual addressing
In addition ROM code is totally relocatable and easy to
access which allows a significant reduction in hardware and
software cost
Software Processor Concept The Series 32000 architec-
ture allows future expansions of the instruction set that can
be executed by special slave processors acting as exten-
sions to the CPU This concept of slave processors is
unique to the Series 32000 architecture It allows software
compatibility even for future components because the slave
hardware is transparent to the software With future ad-
vances in semiconductor technology the slaves can be
physically integrated on the CPU chip itself
To summarize the architectural features cited above pro-
vide three primary performance advantages and character-
istics
 High-Level Language Support
 Easy Future Growth Path
 Application Flexibility
1 1 NS32FX16 SPECIAL FEATURES
In addition to the above Series 32000 features the
NS32FX16 provides features that make the device extreme-
ly attractive for a wide range of applications where graphics
support low chip count and low power consumption are
required
The most relevant of these features are the enhanced Digi-
tal Signal Processing performance which makes the chip
very attractive for facsimile applications and the graphics
support capabilities that can be used in applications such
as printers CRT terminals and other varieties of display
systems where text and graphics are to be handled
Graphics support is provided by eighteen instructions that
allow operations such as BITBLT data compression expan-
sion fills and line drawing to be performed very efficiently
In addition the device can be easily interfaced to an exter-
nal BITBLT Processing Unit (BPU) for high BITBLT perform-
ance
The NS32FX16 allows systems to be built with a relatively
small amount of random logic The bus is highly optimized
to allow simple interfacing to a large variety of DRAMs and
peripheral devices All the relevant bus access signals and
clock signals are generated on-chip The cycle extension
logic is also incorporated on-chip
The device is fabricated in a low-power high speed CMOS
technology It also includes a power-save feature that al-
lows the clock to be slowed down under software control
thus minimizing the power consumption This feature can be
used in those applications where power saving during peri-
ods of low performance demand is highly desirable
The power save feature the DSP Module and the Bus Char-
acteristics are described in the ‘‘Functional Description’’
section A general overview of BITBLT operations and a
description of the graphics support instructions is provided
in Section 2 5 Details on all the NS32FX16 graphics in-
structions can be found in the NS32CG16 Printer Display
Processor Programmer’s Reference Supplement
6

6 Page









NS32FX16-15 pdf, datenblatt
2 0 Architectural Description (Continued)
Note Dashed lines indicate information copied to register during transfer of control between modules
FIGURE 2-10 NS32FX16 Run-Time Environment
TL EE 10818 – 1
2 4 INSTRUCTION SET
2 4 1 General Instruction Format
Figure 2-11 shows the general format of a Series 32000
instruction The Basic Instruction is one to three bytes long
and contains the Opcode and up to two 5-bit General Ad-
dressing Mode (‘‘Gen’’) fields Following the Basic Instruc-
tion field is a set of optional extensions which may appear
depending on the instruction and the addressing modes se-
lected
Index Bytes appear when either or both Gen fields specify
Scaled Index In this case the Gen field specifies only the
Scale Factor (1 2 4 or 8) and the Index Byte specifies
which General Purpose Register to use as the index and
which addressing mode calculation to perform before index-
ing
Following Index Bytes come any displacements (addressing
constants) or immediate values associated with the select-
ed addressing modes Each Disp lmm field may contain
one of two displacements or one immediate value The size
of a Displacement field is encoded within the top bits of that
field as shown in Figure 2-13 with the remaining bits inter-
preted as a signed (two’s complement) value The size of an
immediate value is determined from the Opcode field Both
Displacement and Immediate fields are stored most-signifi-
cant byte first Note that this is different from the memory
representation of data (Section 2 2)
Some instructions require additional ‘‘implied’’ immediates
and or displacements apart from those associated with ad-
dressing modes Any such extensions appear at the end of
the instruction in the order that they appear within the list of
operands in the instruction definition (Section 2 4 3)
TL EE 10818 – 3
FIGURE 2-12 Index Byte Format
FIGURE 2-11 General Instruction Format
12
TL EE 10818 – 2

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