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NM93CS66 Schematic ( PDF Datasheet ) - Fairchild

Teilenummer NM93CS66
Beschreibung (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM with Data Protect and Sequential Read
Hersteller Fairchild
Logo Fairchild Logo 




Gesamt 16 Seiten
NM93CS66 Datasheet, Funktion
February 2000
NM93CS66
(MICROWIRE™ Bus Interface) 4096-Bit Serial EEPROM
with Data Protect and Sequential Read
General Description
NM93CS66 is a 4096-bit CMOS non-volatile EEPROM organized
as 256 x 16-bit array. This device features MICROWIRE interface
which is a 4-wire serial bus with chipselect (CS), clock (SK), data
input (DI) and data output (DO) signals. This interface is compat-
ible to many of standard Microcontrollers and Microprocessors.
NM93CS66 offers programmable write protection to the memory
array using a special register called Protect Register. Selected
memory locations can be protected against write by programming
this Protect Register with the address of the first memory location
to be protected (all locations greater than or equal to this first
address are then protected from further change). Additionally, this
address can be “permanently locked” into the device, making all
future attempts to change data impossible. In addition this device
features “sequential read”, by which, entire memory can be read
in one cycle instead of multiple single byte read cycles. There are
10 instructions implemented on the NM93CS66, 5 of which are for
memory operations and the remaining 5 are for Protect Register
operations. This device is fabricated using Fairchild Semiconduc-
tor floating-gate CMOS process for high reliability, high endurance
and low power consumption.
“LZ” and “L” versions of NM93CS66 offer very low standby current
making them suitable for low power applications. This device is offered
in both SO and TSSOP packages for small space considerations.
Features
I Wide VCC 2.7V - 5.5V
I Programmable write protection
I Sequential register read
I Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
I No Erase instruction required before Write instruction
I Self timed write cycle
I Device status during programming cycles
I 40 year data retention
I Endurance: 1,000,000 data changes
I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
Functional Diagram
CS
SK
DI
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL LOGIC
AND CLOCK
GENERATORS
ADDRESS
REGISTER
PROTECT
REGISTER
COMPARATOR
AND
WRITE ENABLE
VCC
PRE
PE
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
DECODER
EEPROM ARRAY
16
READ/WRITE AMPS
16
DATA IN/OUT REGISTER
16 BITS
DO DATA OUT BUFFER
VSS
© 1999 Fairchild Semiconductor Corporation
NM93CS66 Rev. F.2
1
www.fairchildsemi.com






NM93CS66 Datasheet, Funktion
Functional Description
A typical Microwire cycle starts by first selecting the device
(bringing the CS signal high). Once the device is selected, a valid
Start bit (1) should be issued to properly recognize the cycle.
Following this, the 2-bit opcode of appropriate instruction should
be issued. After the opcode bits, the 8-bit address information
should be issued. For certain instructions, some (or all) of these
8 bits are dont care values (can be 0or 1), but they should still
be issued. Following the address information, depending on the
instruction (WRITE and WRALL), 16-Bit data is issued. Other-
wise, depending on the instruction (READ and PRREAD), the
device starts to drive the output data on the DO line. Other
instructions perform certain control functions and do not deal with
data bits. The Microwire cycle ends when the CS signal is brought
low. However during certain instructions, falling edge of the CS
signal initiates an internal cycle (Programming), and the device
remains busy till the completion of the internal cycle. Each of the
10 instructions is explained in detail in the following sections.
Memory Instructions
Following five instructions, READ, WEN, WRITE, WRALL and
WDS are specific to operations intended for memory array. The
PRE pin should be held low during these instructions.
1) Read and Sequential Read (READ)
READ instruction allows data to be read from a selected location
in the memory array. Input information (Start bit, Opcode and
Address) for this instruction should be issued as listed under
Table1. Upon receiving a valid input information, decoding of the
opcode and the address is made, followed by data transfer from
the selected memory location into a 16-bit serial-out shift register.
This 16-bit data is then shifted out on the DO pin. D15 bit (MSB)
is shifted out first and D0 bit (LSB) is shifted out last. A dummy-bit
(logical 0) precedes this 16-bit data output string. Output data
changes are initiated on the rising edge of the SK clock. After
reading the 16-bit data, the CS signal can be brought low to end
the Read cycle. The PRE pin should be held low during this cycle.
Refer Read cycle diagram.
This device also offers sequential memory readoperation to
allow reading of data from the additional memory locations instead
of just one location. It is started in the same manner as normal read
but the cycle is continued to read further data (instead of terminat-
ing after reading the first 16-bit data). After providing 16-bit data,
the device automatically increments the address pointer to the
next location and continues to provide the data from that location.
Any number of locations can be read out in this manner, however,
after reading out from the last location, the address pointer points
back to the first location. If the cycle is continued further, data will
be read from this first location onward. In this mode of read, the
dummy-bit is present only when the very first data is read (like
normal read cycle) and is not present on subsequent data reads.
The PRE pin should be held low during this cycle. Refer Sequen-
tial Read cycle diagram.
2) Write Enable (WEN)
When VCC is applied to the part, it powers upin the Write Disable
(WDS) state. Therefore, all programming operations (for both
memory array and Protect Register) must be preceded by a Write
Enable (WEN) instruction. Once a Write Enable instruction is
executed, programming remains enabled until a Write Disable
(WDS) instruction is executed or VCC is completely removed from
the part. Input information (Start bit, Opcode and Address) for this
WEN instruction should be issued as listed under Table1. The
device becomes write-enabled at the end of this cycle when the
CS signal is brought low. The PRE pin should be held low during
this cycle. Execution of a READ instruction is independent of WEN
instruction. Refer Write Enable cycle diagram.
3) Write (WRITE)
WRITE instruction allows write operation to a specified location in
the memory with a specified data. This instruction is valid only
when the following are true:
I Device is write-enabled (Refer WEN instruction)
I Address of the write location is not write-protected
I PE pin is held high during this cycle
I PRE pin should be held low during this cycle
Input information (Start bit, Opcode, Address and Data) for this
WRITE instruction should be issued as listed under Table1. After
inputting the last bit of data (D0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
The status of the internal programming cycle can be polled at any
time by bringing the CS signal high again, after tCS interval. When
CS signal is high, the DO pin indicates the READY/BUSY status
of the chip. DO = logical 0 indicates that the programming is still
in progress. DO = logical 1 indicates that the programming is
finished and the device is ready for another instruction. It is not
required to provide the SK clock during this status polling. While
the device is busy, it is recommended that no new instruction be
issued. Refer Write cycle diagram.
It is also recommended to follow this instruction (after the device
becomes READY) with a Write Disable (WDS) instruction to
safeguard data against corruption due to spurious noise, inadvert-
ent writes etc.
4) Write All (WRALL)
Write all (WRALL) instruction is similar to the Write instruction
except that WRALL instruction will simultaneously program all
memory locations with the data pattern specified in the instruction.
This instruction is valid only when the following are true:
I Protect Register has been cleared (Refer PRCLEAR
instruction)
I Device is write-enabled (Refer WEN instruction)
I PE pin is held high during this cycle
I PRE pin should be held low during this cycle
Input information (Start bit, Opcode, Address and Data) for this
WRALL instruction should be issued as listed under Table1. After
inputting the last bit of data (D0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. Refer Write All
cycle diagram.
NM93CS66 Rev. F.2
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NM93CS66 pdf, datenblatt
Timing Diagrams (Continued)
PROTECT REGISTER CLEAR CYCLE (PRCLEAR)
;;;;;;;;;
PRE ;;;;;;;;;
PE ;;;;;;;;;
tCS
CS
SK
1 1 1 A7 A6
A1
DI
Start Opcode
Bit Bits(2) High - Z
DO
93CS66:
Address bits pattern -> 1-1-1-1-1-1-1-1
Address
Bits(8)
A0
tWP
Ready
Busy
PROTECT REGISTER WRITE CYCLE (PRWRITE)
;;;;;;;;;
PRE ;;;;;;;;;
PE ;;;;;;;;;
tCS
CS
SK
1 0 1 A7 A6
A1
DI
Start Opcode
Bit Bits(2) High - Z
DO
93CS66:
Address bits pattern -> User defined
Address
Bits(8)
A0
tWP
Ready
Busy
PROTECT REGISTER DISABLE CYCLE (PRDS)
;;;;;;;;;
PRE ;;;;;;;;;
PE ;;;;;;;;;
tCS
CS
SK
1 0 0 A7 A6
A1
DI
Start Opcode
Address
Bit Bits(2) High - Z Bits(8)
DO
93CS66:
Address bits pattern -> 0-0-0-0-0-0-0-0
A0
tWP
Ready
Busy
NM93CS66 Rev. F.2
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