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8Q1024K8SRAM Schematic ( PDF Datasheet ) - Aeroflex Circuit Technology

Teilenummer 8Q1024K8SRAM
Beschreibung high-performance 1M byte (8Mbit) CMOS static RAM
Hersteller Aeroflex Circuit Technology
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Gesamt 15 Seiten
8Q1024K8SRAM Datasheet, Funktion
Standard Products
QCOTSTM UT8Q1024K8 SRAM
Data Sheet
January, 2003
FEATURES
‰ 25ns maximum (3.3 volt supply) address access time
‰ Dual cavity package contains two (2) 512K x 8 industry-
standard asynchronous SRAMs; the control architecture
allows operation as an 8-bit data width
‰ TTL compatible inputs and output levels, three-state
bidirectional data bus
‰ Typical radiation performance
- Total dose: 50krad(Si)
- SEL Immune >80 MeV-cm2/mg
- LETTH(0.25) = >10 MeV-cm2/mg
- Saturated Cross Section cm2 per bit, 5.0E-9
- <1E-8 errors/bit-day, Adams 90% geosynchronous
heavy ion
‰ Packaging options:
- 44-lead bottom brazed dual CFP (BBTFP) (4.6 grams)
‰ Standard Microcircuit Drawing 5962-01532
- QML T and Q compliant part
INTRODUCTION
The QCOTSTM UT8Q1024K8 Quantified Commercial Off-the-
Shelf product is a high-performance 1M byte (8Mbit) CMOS
static RAM built with two individual 524,288 x 8 bit SRAMs
with a common output enable. Memory access and control is
provided by an active LOW chip enable (En), an active LOW
output enable (G). This device has a power-down feature that
reduces power consumption by more than 90% when deselected.
Writing to each memory is accomplished by taking one of the
chip enable (En) inputs LOW and write enable (Wn) inputs
LOW. Data on the I/O pins is then written into the location
specified on the address pins (A0 through A18). Reading from
the device is accomplished by taking one of the chip enable (En)
and output enable (G) LOW while forcing write enable (Wn)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
Only one SRAM can be read or written at a time.
The input/output pins are placed in a high impedance state when
the device is deselected (En HIGH), the outputs are disabled (G
HIGH), or during a write operation (En LOW and Wn LOW).
A(18:0)
G
E1 W1
E0 W0
512K x 8
512K x 8
DQ(7:0)
Figure 1. UT8Q1024K8 SRAM Block Diagram
1






8Q1024K8SRAM Datasheet, Funktion
AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)*
(-40°C to +125°C) (VDD = 3.3V + 0.3)
SYMBOL
PARAMETER
tAVAV 1
Read cycle time
tAVQV
Read access time
tAXQX 2
Output hold time
tGLQX2
G-controlled Output Enable time
tGLQV
G-controlled Output Enable time (Read Cycle 3)
tGHQZ2
G-controlled output three-state time
tETQX2,3
En-controlled Output Enable time
tETQV3
En-controlled access time
tEFQZ1,2,4
En-controlled output three-state time
MIN
25
3
0
3
Notes: * Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Functional test.
2. Three-state is defined as a 300mV change from steady-state output voltage.
3. The ET (enable true) notation refers to the falling edge of En. SEU immunity does not affect the read parameters.
4. The EF (enable false) notation refers to the rising edge of En. SEU immunity does not affect the read parameters.
MAX
25
10
10
25
10
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
High Z to Active Levels
Active to High Z Levels
VLOAD + 300mV
VLOAD
{
{
VLOAD - 300mV
Figure 3. 3-Volt SRAM Loading
VH - 300mV
}
}
VL + 300mV
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8Q1024K8SRAM pdf, datenblatt
PACKAGING
1. All exposed metalized areas must be plated per MIL-PRF-38535.
2. The lid is electrically connected to VSS.
3. Index mark configuration is optional.
4. Total weight is approx. 4.6 g.
Figure 9. 44-lead bottom brazed dual CFP (BBTFP) package
12

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