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87C196LA Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer 87C196LA
Beschreibung CHMOS 16-BIT MICROCONTROLLER
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 21 Seiten
87C196LA Datasheet, Funktion
PRODUCT PREVIEW
87C196LA
CHMOS 16-BIT MICROCONTROLLER
Automotive
s 20 MHz operation
s 24 Kbytes of on-chip OTPROM
s 768 bytes of on-chip register RAM
s Register-to-register architecture
s Peripheral transaction server (PTS)
with high-speed, microcoded interrupt
service routines
s Six-channel/10-bit A/D with sample and
hold
s High-speed event processor array
— Six capture/compare channels
— Two compare-only channels
— Two 16-bit software timers
16 MHz standard; 20 MHz is speed premium
s Full-duplex serial I/O port with
dedicated baud-rate generator
s Enhanced full-duplex, synchronous
serial I/O port (SSIO)
s Programmable 8- or 16-bit external bus
s Optional clock doubler with
programmable clock output signal
s SFR register that indicates the source
of the last reset
s Design enhancements for EMI
reduction
s Oscillator failure detection circuitry
s Watchdog timer (WDT)
s 40° C to +125° C ambient temperature
s 52-pin PLCC package
NOTE
This datasheet contains information on products in the design phase of development.
The specifications are subject to change without notice. Verify with your local Intel sales
office that you have the latest datasheet before finalizing a design.
The 87C196LA is a high-performance 16-bit microcontroller. The 87C196LA is composed of a high-speed
core with the following peripherals: an asynchronous/synchronous serial I/O port (8096 compatible) with a
dedicated 16-bit baud-rate generator; an additional synchronous serial I/O port with full duplex master/slave
transceivers; a six-channel A/D converter with sample and hold; a flexible timer/counter structure with
prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O for capture
and compare (called event processor array) with 200 ns resolution and double buffered inputs; and a sophis-
ticated, prioritized interrupt structure with programmable peripheral transaction server (PTS). The clock
doubler circuitry and oscillator output signal enable a 4 MHz resonator to achieve the same internal clock
speed as a more costly 8 MHz resonator in previous applications. This same circuitry can drive other devices
where a separate resonator was required in the past. Another cost-savings feature is the fact that the I/O
ports are driven low at reset, avoiding the need for pull-up resistors.
COPYRIGHT © INTEL CORPORATION, 1996
October 1996
Order Number: 272806-001






87C196LA Datasheet, Funktion
87C196LA — AUTOMOTIVE
Table 2. 87C196LA 52-pin Package Pin Assignments
Pin Name
Pin Name
Pin Name
1 VSS1
2 P5.0 / ADV# / ALE
19 AD3 / P3.3 / PBUS.3
20 AD2 / P3.2 / PBUS.2
37 P0.6 / ACH6 / PMODE.2
38 P0.7 / ACH7 / PMODE.3
3 VSS
4 VPP
5 P5.3 / RD#
21 AD1 / P3.1 / PBUS.1
22 AD0 / P3.0 / PBUS.0
23 RESET#
39 ANGND
40 VREF
41 P1.3 / EPA3
6 P5.2 / PLLEN / WR# / WRL# 24 EA#
42 P1.2 / EPA2 / T2DIR
7 AD15 / P4.7 / PBUS.15
8 AD14 / P4.6 / PBUS.14
9 AD13 / P4.5 / PBUS.13
25 VSS1
26 VCC
27 P2.0 / TXD / PVER
43 P1.1 / EPA1
44 P1.0 / EPA0 / T2CLK
45 P6.0 / EPA8 / COMP0
10 AD12 / P4.4 / PBUS.12
28 P2.1 / RXD / PALE#
46 P6.1 / EPA9 / COMP1
11 AD11 / P4.3 / PBUS.11
29 P2.2 / EXTINT / PROG#
47 P6.4 / SC0
12 AD10 / P4.2 / PBUS.10
30 P2.4 / AINC#
48 P6.5 / SD0
13 AD9 / P4.1 / PBUS.9
31 P2.6 / CPVER
49 P6.6 / SC1
14 AD8 / P4.0 / PBUS.8
32 P2.7 / CLKOUT / PACT#
50 P6.7 / SD1
15 AD7 / P3.7 / PBUS.7
33 P0.2 / ACH2
51 XTAL2
16 AD6 / P3.6 / PBUS.6
34 P0.3 / ACH3
52 XTAL1
17 AD5 / P3.5 / PBUS.5
35 P0.4 / ACH4 / PMODE.0
18 AD4 / P3.4 / PBUS.4
36 P0.5 / ACH5 / PMODE.1
6 PRODUCT PREVIEW

6 Page









87C196LA pdf, datenblatt
87C196LA — AUTOMOTIVE
Name
PROG#
PVER
RD#
RESET#
RXD
SC1:0
SD1:0
Type
I
O
O
I/O
I/O
I/O
I/O
Table 4. Signal Descriptions (Continued)
Description
Programming Start
Duringprogramming, a falling edge latches data on the programming bus and
begins programming, while a rising edge ends programming. The current
location is programmed with the same data as long as PROG# remains
asserted, so the data on the programming bus must remain stable while
PROG# is active.
During a word dump, a falling edge causes the contents of an OTPROM
location to be output on the PBUS, while a rising edge ends the data transfer.
PROG# shares a package pin with P2.2 and EXTINT.
Program Verification
During slave or auto programming, PVER is updated after each programming
pulse. A high output signal indicates successful programming of a location,
while a low signal indicates a detected error.
PVER shares a package pin with P2.0 and TXD.
Read
Read-signal output to external memory. RD# is asserted only during external
memory reads.
RD# shares a package pin with P5.3.
Reset
A level-sensitive reset input to, and an open-drain system reset output from, the
microcontroller. Either a falling edge on RESET# or an internal reset turns on a
pull-down transistor connected to the RESET# pin for 16 state times. In the
powerdown and idle modes, asserting RESET# causes the chip to reset and
return to normal operating mode. After a device reset, the first instruction fetch
is from 2080H.
Receive Serial Data
In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it
functions as either an input or an open-drain output for data.
RXD shares a package pin with P2.1 and PALE#.
Clock Pins for SSIO0 and 1
For handshaking transfers, configure SC1:0 as open-drain outputs.
This pin carries a signal only during receptions and transmissions. When the
SSIO port is idle, the pin remains either high (with handshaking) or low (without
handshaking).
SC0 shares a package pin with P6.4, and SC1 shares a package pin with P6.6.
Data Pins for SSIO0 and 1
These pins are the data I/O pins for SSIO0 and 1. For transmissions, configure
SDx as a complementary output signal. For receptions, configure SDx as a
high-impedance input signal.
SD0 shares a package pin with P6.5, and SD1 shares a package pin with P6.7.
12 PRODUCT PREVIEW

12 Page





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