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87C196JV Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer 87C196JV
Beschreibung Advanced 16-Bit CHMOS Microcontrollers
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
87C196JV Datasheet, Funktion
87C196KR, 87C196JV, 87C196JT,
87C196JR, and 87C196CA Advanced
16-Bit CHMOS Microcontrollers
Automotive
Datasheet
Product Features
s –40°C to +125°C Ambient
s High Performance CHMOS 16-Bit CPU
s Up to 48 Kbytes of On-Chip EPROM
s Up to 1.5 Kbytes of On-Chip Register
RAM
s Up to 512 Bytes of Additional RAM (Code
RAM)
s Register-Register Architecture
s Up to Eight Channel/10-Bit A/D with
Sample/Hold
s Up to 37 Prioritized Interrupt Sources
s Up to Seven 8-Bit (56) I/O Ports
s Full Duplex Serial I/O Port
s Dedicated Baud Rate Generator
s Interprocessor Communication Slave Port
s High Speed Peripheral Transaction Server
(PTS)
s Two 16-Bit Software Timers
s Up to 10 High Speed Capture/Compare
(EPA)
s Full Duplex Synchronous Serial I/O Port
(SSIO)
s Two Flexible 16-Bit Timer/Counters
s Quadrature Counting Inputs
s Flexible 8-/16-Bit External Bus
s Programmable Bus (HLD/HLDA)
s 1.75 µs 16 x 16 Multiply
s 3 µs 32/16 Divide
s 68-Pin and 52-Pin PLCC Packages
s Supports CAN (Controller Area Network)
Specification 2.0 (CA only)
Order Number: 270827-007
April 1998






87C196JV Datasheet, Funktion
87C196KR, JV, JT, JR, CA Microcontrollers — Automotive
Table 1. 87C196Kx and Jx Features Summary
Device
Pins/Package
87C196KR
87C196JV
87C196JT
87C196JR
87C196CA
68-Pin PLCC
52-Pin PLCC
52-Pin PLCC
52-Pin PLCC
68-Pin PLCC
EPROM Reg RAM Code RAM I/O EPA SIO SSIO A/D
16 K
48 K
32 K
16 K
32 K
512
1.5 K
1.0 K
512
1.0 K
256 56 10 Y Y 8
512 41 6 Y Y 6
512 41 6 Y Y 6
256 41 6 Y Y 6
256 38 6 Y Y 6
Refer to the following datasheets for higher frequency versions of devices contained within this
datasheet:
87C196JT 20 MHz Advanced 16-Bit CHMOS Microcontroller datasheet, order #272529
87C196JV 20 MHz Advanced 16-Bit CHMOS Microcontroller datasheet, order #272580.
2.0 Architecture
The 87C196KR, JV, JT, JR, and CA are members of the MCS 96 microcontroller family, have the
same architecture and use the same instruction set as the 80C196KB/KC. Many new features have
been added including:
2.1 CPU Features
Powerdown and Idle Modes
16 MHz Operating Frequency
A High Performance Peripheral Transaction Server (PTS)
Up to 37 Interrupt Vectors
Up to 512 Bytes of Code RAM
Up to 1.5 Kbytes of Register RAM
“Windowing” Allows 8-Bit Addressing to Some 16-Bit Addresses
1.75 µs 16 x 16 Multiply
3 µs 32/16 Divide
Oscillator Fail Detect
2.2 Peripheral Features
Programmable A/D Conversion and S/H Times
Up to 10 Capture/Compare I/O with 2 Flexible Timers
Synchronous Serial I/O Port for Full Duplex Serial I/O
6 Datasheet

6 Page









87C196JV pdf, datenblatt
87C196KR, JV, JT, JR, CA Microcontrollers — Automotive
Table 2. Pin Descriptions (Sheet 1 of 2)
VCC
VSS
Symbol
VREF
VPP
ANGND
XTAL1
XTAL2
P2.7/CLKOUT
RESET#
P5.7/BUSWIDTH
NMI
P5.1/INST
EA#
P5.0/ALE/ADV#
P5.3/RD#
P5.2/WR#/WRL#
Name and Function
Main supply voltage (+5 V).
Digital circuit ground (0 V). There are three VSS pins, all of which MUST be
connected to a single ground plane.
Reference for the A/D converter (+5 V). VREF is also the supply voltage to the
analog portion of the A/D converter and the logic used to read Port 0. Must be
connected for A/D and Port 0 to function.
Programming voltage for the EPROM parts. It should be +12.5 V for programming.
It is also the timing pin for the return from powerdown circuit. Connect this pin with
a 1 µF capacitor to VSS and a 1 Mresistor to VCC. If this function is not used, VPP
may be tied to VCC.
Reference ground for the A/D converter. Must be held at nominally the same
potential as VSS.
Input of the oscillator inverter and the internal clock generator.
Output of the oscillator inverter.
Output of the internal clock generator. The frequency is ½ the oscillator frequency.
It has a 50% duty cycle. Also LSIO pin when not used as CLKOUT.
Reset input to the chip. Input low for at least 16 state times will reset the chip. The
subsequent low to high transition resynchronizes CLKOUT and commences a 10-
state time sequence in which the PSW is cleared, bytes are read from 2018H and
201AH loading the CCBs, and a jump to location 2080H is executed. Input high for
normal operation. RESET# has an internal pullup.
Input for bus width selection. If CCR bit 1 is a one and CCR1 bit 2 is a one, this pin
dynamically controls the Bus width of the bus cycle in progress. If BUSWIDTH is
low, an 8-bit cycle occurs. If BUSWIDTH is high, a 16-bit cycle occurs. If CCR bit 1
is “0” and CCR1 bit 2 is “1”, all bus cycles are 8-bit; if CCR bit 1 is “1” and CCR1 bit
2 is “0”, all bus cycles are 16-bit. CCR bit 1 =”0'' and CCR1 bit 2 = “0” is illegal.
Also an LSIO pin when not used as BUSWIDTH.
A positive transition causes a non-maskable interrupt vector through memory
location 203EH.
Output high during an external memory read indicates the read is an instruction
fetch. INST is valid throughout the bus cycle. INST is active only during external
memory fetches. During internal [EP]ROM fetches INST is held low. Also LSIO
when not INST.
Input for memory select (External Access). EA# equal to a high causes memory
accesses within the [EP]ROM address space to be directed to on-chip EPROM/
ROM. EA# equal to a low causes accesses to these locations to be directed to off-
chip memory. EA# = +12.5 V causes execution to begin in the Programming
Mode. EA# latched at reset.
Address Latch Enable or Address Valid output, as selected by CCR. Both pin
options provide a latch to demultiplex the address from the address/data bus.
When the pin is ADV#, it goes inactive (high) at the end of the bus cycle. ADV#
can be used as a chip select for external memory. ALE/ADV# is active only during
external memory accesses. Also LSIO when not used as ALE.
Read signal output to external memory. RD# is active only during external memory
reads. LSIO when not used as RD#.
Write and Write Low output to external memory, as selected by the CCR, WR# will
go low for every external write, while WRL# will go low only for external writes
where an even byte is being written. WR#/WRL# is active during external memory
writes. Also an LSIO pin when not used as WR#/WRL#.
12 Datasheet

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