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MMSF7P03HD Schematic ( PDF Datasheet ) - Motorola Semiconductors

Teilenummer MMSF7P03HD
Beschreibung SINGLE TMOS POWER MOSFET 30 VOLTS
Hersteller Motorola Semiconductors
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Gesamt 10 Seiten
MMSF7P03HD Datasheet, Funktion
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MMSF7P03HD/D
Designer's Data Sheet
Medium Power Surface Mount Products
TMOS Single P-Channel
Field Effect Transistors
Single HDTMOS are an advanced series of power MOSFETs
which utilize Motorola’s High Cell Density TMOS process.
HDTMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc–dc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives.
Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive — Can Be Driven by Logic ICs
Miniature SO–8 Surface Mount Package — Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Mounting Information for SO–8 Package Provided
G
MMSF7P03HD
Motorola Preferred Device
SINGLE TMOS
POWER MOSFET
30 VOLTS
RDS(on) = 35 mW
D
S
CASE 751–05, Style 13
SO–8
Source
Source
Source
Gate
18
27
36
45
Top View
Drain
Drain
Drain
Drain
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
Gate–to–Source Voltage — Continuous
Drain Current — Continuous @ TA = 25°C
Drain Current — Single Pulse (tp 10 µs)
Source Current — Continuous @ TA = 25°C
Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy – STARTING TJ = 25°C
W(VDD = 30 Vdc, VGS = 5.0 Vdc, VDS = 32 Vdc, IL = 10 Apk, L = 10 mH, RG = 25 )
Thermal Resistance — Junction–to–Ambient
Maximum Temperature for Soldering
VDSS
VGS
ID
IDM
IS
PD
TJ, Tstg
EAS
30
± 20
7.0
50
2.3
2.5
– 55 to 150
5000
Vdc
Vdc
Adc
Apk
Adc
Watts
°C
mJ
RθJA
T
50 °C/W
260 °C
DEVICE MARKING
S7P03
(1) When mounted on 1 inch square FR–4 or G–10 (VGS = 10 V @ 10 seconds)
ORDERING INFORMATION
Device
Reel Size
Tape Width
Quantity
MMSF7P03HDR2
13
12 mm embossed tape
2500 units
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Preferred devices are Motorola recommended choices for future use and best overall value.
Designer’s and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
REV 2
©MMoottoororolal,aInTc.M19O9S7 Power MOSFET Transistor Device Data
1






MMSF7P03HD Datasheet, Funktion
MMSF7P03HD
di/dt = 300 A/µs
Standard Cell Density
trr
High Cell Density
trr
ta tb
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curve (Figure
12) defines the maximum simultaneous drain–to–source vol-
tage and drain current that a transistor can handle safely
when it is forward biased. Curves are based upon maximum
peak junction temperature and a case temperature (TC) of
25°C. Peak repetitive pulsed power limits are determined by
using the thermal response data in conjunction with the pro-
cedures discussed in AN569, “Transient Thermal Resistance
– General Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem-
perature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
100
VGS = 12 V
SINGLE PULSE
10 TA = 25°C
10 ms
1 ms
1.0
dc
0.1
0.01
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1.0 10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
100
5000
4500
4000 ID = 7.0 A
3500
3000
2500
2000
1500
1000
500
0
25
45 65 85 105 125
TJ, STARTING JUNCTION TEMPERATURE (°C)
145
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
6 Motorola TMOS Power MOSFET Transistor Device Data

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