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MMSF5N03HD Schematic ( PDF Datasheet ) - Motorola Semiconductors

Teilenummer MMSF5N03HD
Beschreibung SINGLE TMOS POWER MOSFET 5.0 AMPERES 30 VOLTS
Hersteller Motorola Semiconductors
Logo Motorola Semiconductors Logo 




Gesamt 10 Seiten
MMSF5N03HD Datasheet, Funktion
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MMSF5N03HD/D
Designer's Data Sheet
Medium Power Surface Mount Products
TMOS Single N-Channel
Field Effect Transistors
MiniMOSdevices are an advanced series of power MOSFETs
which utilize Motorola’s High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain–to–source diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc–dc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.
G
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive — Can Be Driven by Logic ICs
Miniature SO–8 Surface Mount Package — Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for SO–8 Package Provided
MMSF5N03HD
Motorola Preferred Device
SINGLE TMOS
POWER MOSFET
5.0 AMPERES
30 VOLTS
RDS(on) = 0.040 OHM
D
S
CASE 751–05, Style 13
SO–8
N–C
Source
Source
Gate
18
27
36
45
Top View
Drain
Drain
Drain
Drain
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 M)
Gate–to–Source Voltage — Continuous
Drain Current — Continuous @ TA = 25°C
Drain Current — Continuous @ TA = 100°C
Drain Current — Single Pulse (tp 10 µs)
Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 4.0 mH, RG = 25 )
Thermal Resistance — Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
DEVICE MARKING
Symbol
VDSS
VDGR
VGS
ID
ID
IDM
PD
TJ, Tstg
EAS
Value
30
30
± 20
6.5
4.4
33
2.5
– 55 to 150
450
Unit
Vdc
Vdc
Vdc
Adc
Apk
Watts
°C
mJ
RθJA
TL
50 °C/W
260 °C
S5N03
(1) Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided), 10 sec. max.
ORDERING INFORMATION
Device
Reel Size
Tape Width
Quantity
MMSF5N03HDR2
13
12 mm embossed tape
2500 units
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, HDTMOS and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 5
©MMoottoororolal,aInTc.M19O9S6 Power MOSFET Transistor Device Data
1






MMSF5N03HD Datasheet, Funktion
MMSF5N03HD
di/dt = 300 A/µs
Standard Cell Density
trr
High Cell Density
trr
ta tb
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance – Gen-
eral Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem-
perature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
100
VGS = 10 V
SINGLE PULSE
10 TC = 25°C
100 µs
1 ms
10 ms
1 dc
RDS(on) LIMIT
0.1
THERMAL LIMIT
PACKAGE LIMIT
Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06”
thick single sided), 10s max.
0.01
0.1 1
10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
100
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
450
ID = 15 A
300
150
0
25 50 75 100 125 150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
6 Motorola TMOS Power MOSFET Transistor Device Data

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