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PDF MMSF3300 Data sheet ( Hoja de datos )
| Número de pieza | MMSF3300 | |
| Descripción | SINGLE TMOS POWER MOSFET 30 VOLTS | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
WaveFET™
Power Surface Mount Products
HDTMOS Single N-Channel
Field Effect Transistor
™
WaveFET™ devices are an advanced series of power MOSFETs which utilize Motorola’s
latest MOSFET technology process to achieve the lowest possible on–resistance per silicon
area. They are capable of withstanding high energy in the avalanche and commutation
modes and the drain–to–source diode has a very low reverse recovery time. WaveFET™
devices are designed for use in low voltage, high speed switching applications where power
efficiency is important. Typical applications are dc–dc converters, and power management
in portable and battery powered products such as computers, printers, cellular and cordless
phones. They can also be used for low voltage motor controls in mass storage products
such as disk drives and tape drives. The avalanche energy is specified to eliminate the
guesswork in designs where inductive loads are switched and offer additional safety margin
against unexpected voltage transients.
• Characterized Over a Wide Range of Power Ratings
• Ultralow RDS(on) Provides Higher Efficiency and
Extends Battery Life in Portable Applications
• Logic Level Gate Drive — Can Be Driven by
Logic ICs
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, With Soft Recovery
• IDSS Specified at Elevated Temperature
• Avalanche Energy Specified
• Miniature SO–8 Surface Mount Package —
Saves Board Space
G
D
S
Order this document
by MMSF3300/D
MMSF3300
SINGLE TMOS
POWER MOSFET
30 VOLTS
RDS(on) = 12.5 mW
CASE 751– 06, Style 12
SO–8
Source
Source
Source
Gate
18
27
36
45
TOP VIEW
Drain
Drain
Drain
Drain
MAXIMUM RATINGS (TJ = 25°C unless otherwise specified)
Parameter
Drain–to–Source Voltage
Drain–to–Gate Voltage
Gate–to–Source Voltage
Gate–to–Source Operating Voltage
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, L = 18.8 mH, IL(pk) = 7.3 A, VDS = 30 Vdc)
Symbol
VDSS
VDGR
VGS
VGS
TJ, Tstg
EAS
Value
30
30
± 20
± 16
– 55 to 150
500
Unit
Vdc
Vdc
Vdc
Vdc
°C
mJ
DEVICE MARKING
ORDERING INFORMATION
S3300
Device
MMSF3300R2
Reel Size
13″
Tape Width
12 mm embossed tape
This document contains information on a new product. Specifications and information herein are subject to change without notice.
HDTMOS and WaveFET are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Quantity
2500 units
REV 3
©MMoottoororolal,aInTc.M19O9S8 Power MOSFET Transistor Device Data
1
1 page  
POWER MOSFET SWITCHING
MMSF3300
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
4000 VDS = 0 VGS = 0
3500 Ciss
3000
2500 Crss
2000
1500
1000
500
0
10
505
VGS VDS
10 15
TJ = 25°C
Ciss
Coss
Crss
20 25 30
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
Motorola TMOS Power MOSFET Transistor Device Data
5
5 Page 
PACKAGE DIMENSIONS
MMSF3300
AD
8
E
1
5
H
4
0.25 M B M
Be
h X 45 _
q
CA
SEATING
PLANE
A1 B
0.10
0.25 M C B S A S
C
L
CASE 751–06
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
MILLIMETERS
DIM MIN MAX
A 1.35 1.75
A1 0.10 0.25
B 0.35 0.49
C 0.19 0.25
D 4.80 5.00
E 3.80 4.00
e 1.27 BSC
H 5.80 6.20
h 0.25 0.50
L 0.40 1.25
q 0_ 7_
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
Motorola TMOS Power MOSFET Transistor Device Data
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MMSF3300.PDF ] | |
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