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MMSF2P02E Schematic ( PDF Datasheet ) - Motorola Semiconductors

Teilenummer MMSF2P02E
Beschreibung SINGLE TMOS POWER MOSFET 2.5 AMPERES 20 VOLTS
Hersteller Motorola Semiconductors
Logo Motorola Semiconductors Logo 




Gesamt 8 Seiten
MMSF2P02E Datasheet, Funktion
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MMSF2P02E/D
Designer's Data Sheet
Medium Power Surface Mount Products
TMOS Single P-Channel
Field Effect Transistors
MiniMOSdevices are an advanced series of power MOSFETs
which utilize Motorola’s TMOS process. These miniature surface
mount MOSFETs feature ultra low RDS(on) and true logic level
performance. They are capable of withstanding high energy in the
avalanche and commutation modes and the drain–to–source diode
has a low reverse recovery time. MiniMOS devices are designed
for use in low voltage, high speed switching applications where
power efficiency is important. Typical applications are dc–dc
converters, and power management in portable and battery
powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor
controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.
G
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive — Can Be Driven by Logic ICs
Miniature SO–8 Surface Mount Package — Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed
Avalanche Energy Specified
Mounting Information for SO–8 Package Provided
IDSS Specified at Elevated Temperature
MMSF2P02E
Motorola Preferred Device
SINGLE TMOS
POWER MOSFET
2.5 AMPERES
20 VOLTS
RDS(on) = 0.250 OHM
D
S
CASE 751–05, Style 13
SO–8
N–C
Source
Source
Gate
18
27
36
45
Top View
Drain
Drain
Drain
Drain
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)(1)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
Gate–to–Source Voltage — Continuous
Drain Current — Continuous @ TA = 25°C (2)
Drain Current — Continuous @ TA = 100°C
Drain Current — Single Pulse (tp 10 µs)
Total Power Dissipation @ TA = 25°C(2)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 20 Vdc, VGS = 5.0 Vdc, IL = 6.0 Apk, L = 12 mH, RG = 25 )
Thermal Resistance — Junction to Ambient(2)
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
VDSS
VGS
ID
ID
IDM
PD
TJ, Tstg
EAS
20
± 20
2.5
1.7
13
2.5
– 55 to 150
216
Vdc
Vdc
Adc
Apk
Watts
°C
mJ
RθJA
TL
50 °C/W
260 °C
DEVICE MARKING
S2P02
(1) Negative sign for P–Channel device omitted for clarity.
(2) Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided), 10 sec. max.
ORDERING INFORMATION
Device
Reel Size
Tape Width
Quantity
MMSF2P02ER2
13
12 mm embossed tape
2500 units
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, HDTMOS and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a registered trademark of Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 4
©MMoottoororolal,aInTc.M19O9S6 Power MOSFET Transistor Device Data
1






MMSF2P02E Datasheet, Funktion
MMSF2P02E
IS
tp
di/dt
trr
ta tb
0.25 IS
IS
TIME
Figure 15. Diode Reverse Recovery Waveform
INFORMATION FOR USING THE SO–8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self–align when subjected to a
solder reflow process.
0.060
1.52
0.275
7.0
0.155
4.0
0.024
0.6
0.050
1.270
inches
mm
SO–8 POWER DISSIPATION
The power dissipation of the SO–8 is a function of the input
pad size. This can vary from the minimum pad size for
soldering to the pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature of the die, RθJA, the thermal resistance from the
device junction to ambient; and the operating temperature, TA.
Using the values provided on the data sheet for the SO–8
package, PD can be calculated as follows:
PD =
TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this case
is 2.5 Watts.
PD =
150°C – 25°C
50°C/W
= 2.5 Watts
The 50°C/W for the SO–8 package assumes the
recommended footprint on a glass epoxy printed circuit board
to achieve a power dissipation of 2.5 Watts using the footprint
shown. Another alternative would be to use a ceramic
substrate or an aluminum core board such as Thermal Clad.
Using board material such as Thermal Clad, the power
dissipation can be doubled using the same footprint.
6 Motorola TMOS Power MOSFET Transistor Device Data

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