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PDF 84C84X Data sheet ( Hoja de datos )
| Número de pieza | 84C84X | |
| Descripción | 8-bit microcontrollers with OSD and VST | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Philips Semiconductors
8-bit microcontrollers with OSD and VST
Product specification
84C44X; 84C64X; 84C84X
CONTENTS
1
1.1
1.2
2
2.1
3
4
5
6
7
7.1
8
8.1
8.1.1
8.1.2
8.1.3
9
9.1
9.1.1
9.1.2
9.2
9.3
10
11
12
12.1
12.2
12.3
12.4
12.4.1
12.4.2
12.5
12.6
12.6.1
12.6.2
12.6.3
12.6.4
12.7
12.7.1
12.7.2
12.8
12.8.1
12.8.2
12.9
13
FEATURES
PCF84CXXXA kernel
Derivative features PCA84C640
GENERAL DESCRIPTION
Important
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING INFORMATION
DIFFERENCES
RESET
Power-on-reset
ANALOG CONTROL
6-bit PWM DACs
Pin selection for PWM outputs
Polarity of the PWM outputs
Analog output voltage
VST CONTROL
14-bit PWM DAC
14-bit counter
Data and interface latches
Coarse adjustment
Fine adjustment
AFC INPUT
INPUT/OUTPUT ( I/O)
ON SCREEN DISPLAY
Features
Horizontal display position control
Vertical display position control
Clock generator
RC oscillator
LC oscillator
Display data registers
Display control registers
Derivative register OSDCA
Derivative registers LINE 0A and LINE 0B
Derivative registers LINE 1A and LINE 1B
Derivative register OSDCB
OSD display position
Vertical position
Horizontal position
OSD character size and colour selection
Character size
Colour selection
Character ROM
EMULATION MODE
14
15
16
17
17.1
18
19
19.1
19.1.1
19.1.2
20
21
22
REGISTER MAP
LIMITING VALUES
DC CHARACTERISTICS
AC CHARACTERISTICS
Characteristic curves
PACKAGE OUTLINE
SOLDERING
Plastic dual in-line packages
By dip or wave
Repairing soldered joints
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
October 1994
2
1 page  
Philips Semiconductors
8-bit microcontrollers with OSD and VST
Product specification
84C44X; 84C64X; 84C84X
October 1994
6
5 Page 
Philips Semiconductors
8-bit microcontrollers with OSD and VST
Product specification
84C44X; 84C64X; 84C84X
9 VST CONTROL
9.1 14-bit PWM DAC
The PCA84C640 has one 14-bit PWM DAC output (TDAC)
with a resolution of 16384 levels for Voltage Synthesized
Tuning. The PWM DAC (see Fig.10) consists of:
• 14-bit counter
• Two 7-bit DAC interface data latches (VSTH and VSTL)
• One 14-bit DAC data latch (VSTREG)
• Pulse control.
The polarity of output TDAC is selected with bit P14LVL.
Setting the bit P14LVL to:
• Logic 1, sets the TDAC output to the default polarity
• Logic 0, inverts the TDAC output.
9.1.1 14-BIT COUNTER
The counter is continuously running and is clocked by f0.
The period of the clock, t0 = f--X----T3---A---L-
The repetition time for one complete cycle of the counter:
tr = t0 × 16 384
The repetition time for one cycle of the lower 7-bits of the
counter is:
tsub = t0 × 128
Therefore, the number of tsub periods in a complete
cycle tr is:
N = t--0--t--0×----×-1----61---2-3--8-8---4-- = 128
9.1.2 DATA AND INTERFACE LATCHES
In order to ensure correct operation, interface data latch
VSTH is loaded first and then interface data latch VSTL.
The contents of:
• VSTH are used for coarse adjustment
• VSTL are used for fine adjustment.
At the beginning of the first tsub period following the loading
of VSTL, both data latches are loaded into data latch
VSTREG. After the contents of VSTH and VSTL are
latched into VSTREG, one tsub period is needed to
generate the appropriate pulse pattern.
To ensure correct DAC conversion, two (2) tsub periods
should be allowed before beginning the next sequence.
9.2 Coarse adjustment
The coarse adjustment output (OUT1) is reset to LOW
(inactive) at the start of each tsub period.
It will remain LOW until the time [t0 × (VSTH + 1) ] has
elapsed and then will go HIGH and remain so until the next
tsub period starts.
9.3 Fine adjustment
Fine adjustment is achieved by generating additional
pulses at the start of particular sub-periods (tsubn).
These additional pulses have a width of t0.
The sub-period in which a pulse is added is determined by
the contents of VSTL interface latch.
Table 3 gives the numbers of the tsubn, at the start of which
an additional pulse is generated, depending on the bit in
VSTL being a logic 0. When more than one bit is a logic 0
a combination of additional pulses are generated.
For example, if VSTL = 1111010, which is a combination of
• VSTL = 1111110: sub-period 64, and
• VSTL = 1111011: sub-periods 16, 48, 80, 112,
then additional pulses will be given in sub-periods
16, 48, 64, 80 and 112; this is illustrated in Fig.12.
If VSTH = 0011101, VSTL = 1111010 and P14LVL = 0,
then the TDAC output is as shown in Fig.13.
Table 3 Additional pulse distribution
LOWER 7
BITS (VSTL)
ADDITIONAL PULSE IN
SUB-PERIODS tsubn
111 1110 64
111 1101 32, 96
111 1011 16, 48, 80, 112
111 0111 8, 24, 40, 56, 72, 88, 104, 120
110 1111 4, 12, 20, 28, 36, 44, 52, 60 .... 116, 124
101 1111 2, 6, 10, 14, 18, 22, 26, 30, .... 122, 126
011 1111 1, 3, 5, 7, 9, 11, 13, 15, 17, .... 125, 127
October 1994
12
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 84C84X.PDF ] | |
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