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PDF MM74HC00N Data sheet ( Hoja de datos )
| Número de pieza | MM74HC00N | |
| Descripción | Quad 2-Input NAND Gate | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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February 2008
MM74HC00
Quad 2-Input NAND Gate
Features
■ Typical propagation delay: 8ns
■ Wide power supply range: 2V–6V
■ Low quiescent current: 20µA maximum (74HC Series)
■ Low input current: 1µA maximum
■ Fanout of 10 LS-TTL loads
General Description
The MM74HC00 NAND gates utilize advanced silicon-
gate CMOS technology to achieve operating speeds
similar to LS-TTL gates with the low power consumption
of standard CMOS integrated circuits. All gates have
buffered outputs. All devices have high noise immunity
and the ability to drive 10 LS-TTL loads. The 74HC logic
family is functionally as well as pin-out compatible with
the standard 74LS logic family. All inputs are protected
from damage due to static discharge by internal diode
clamps to VCC and ground.
Ordering Information
Package
Order Number Number
Package Description
MM74HC00M
MM74HC00SJ
MM74HC00MTC
M14A
M14D
MTC14
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC00N
N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Logic Diagram
Top View
©1983 Fairchild Semiconductor Corporation
MM74HC00 Rev. 1.3.0
www.fairchildsemi.com
1 page  
Physical Dimensions
8.75
8.50
7.62
14
6.00
A
8
B
4.00
3.80
0.65
5.60
PIN ONE
INDICATOR
1
1.27
(0.33)
7
0.51
0.35
1.70
1.27
LAND PATTERN RECOMMENDATION
0.25 M C B A
1.75 MAX
1.50
1.25
R0.10
R0.10
8°
0°
SEE DETAIL A
0.25
0.10 C
0.10 C
0.25
0.19
NOTES: UNLESS OTHERWISE SPECIFIED
0.50
0.25
A) THIS PACKAGE CONFORMS TO JEDEC
X 45°
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE FLASH OR BURRS.
D) LANDPATTERN STANDARD:
0.36
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.90
0.50
(1.04)
SEATING PLANE
DETAIL A
SCALE: 20:1
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1983 Fairchild Semiconductor Corporation
MM74HC00 Rev. 1.3.0
5
www.fairchildsemi.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MM74HC00N.PDF ] | |
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