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NM27C512 Schematic ( PDF Datasheet ) - Fairchild

Teilenummer NM27C512
Beschreibung 524 /288-Bit (64K x 8) High Performance CMOS EPROM
Hersteller Fairchild
Logo Fairchild Logo 




Gesamt 10 Seiten
NM27C512 Datasheet, Funktion
July 1998
NM27C512
524,288-Bit (64K x 8) High Performance CMOS EPROM
General Description
The NM27C512 is a high performance 512K UV Erasable Electri-
cally Programmable Read Only Memory (EPROM). It is manufac-
tured using Fairchild’s proprietary CMOS AMG™ EPROM tech-
nology for an excellent combination of speed and economy while
providing excellent reliability.
The NM27C512 provides microprocessor-based systems storage
capacity for portions of operating system and application soft-
ware. Its 90 ns access time provides no wait-state operation with
high-performance CPUs. The NM27C512 offers a single chip
solution for the code storage requirements of 100% firmware-
based equipment. Frequently-used software routines are quickly
executed from EPROM storage, greatly enhancing system utility.
The NM27C512 is configured in the standard JEDEC EPROM
pinout which provides an easy upgrade path for systems which are
currently using standard EPROMs.
The NM27C512 is one member of a high density EPROM Family
which range in densities up to 4 Megabit.
Features
s High performance CMOS
— 90 ns access time
s Fast turn-off for microprocessor compatibility
s Manufacturers identification code
s JEDEC standard pin configuration
— 28-pin PDIP package
— 32-pin chip carrier
— 28-pin CERDIP package
Block Diagram
VCC
GND
VPP
OE
CE/PGM
Output Enable and
Chip Enable Logic
Data Outputs O0 - O7
Output
Buffers
Y Decoder
A0 - A15
Address
Inputs
X Decoder
524,288-Bit
Cell Matrix
AMG is a trademark of WSI, Inc.
© 1998 Fairchild Semiconductor Corporation
1
DS010834-1
www.fairchildsemi.com






NM27C512 Datasheet, Funktion
Turbo Programming Algorithm Flow Chart
VCC = 6.5V VPP = 12.75V
n=0
ADDRESS = FIRST LOCATION
PROGRAM ONE 50µs PULSE
INCREMENT n
DEVICE
FAILED
NO
YES n = 10?
FAIL VERIFY
BYTE
PASS
LAST NO
ADDRESS
?
YES
INCREMENT
ADDRESS
n=0
ADDRESS = FIRST LOCATION
INCREMENT
ADDRESS
VERIFY FAIL
BYTE
PASS
NO LAST
ADDRESS
?
YES
PROGRAM ONE
50 µs
PULSE
CHECK ALL BYTES
1ST: VCC = VPP = 6.0V
2ND: VCC = VPP = 4.3V
Note: The standard National Semiconductor algorithm may also be used but it will take longer programming time.
FIGURE 1.
DS010834-6
6 www.fairchildsemi.com

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