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NM24W16 Schematic ( PDF Datasheet ) - Fairchild

Teilenummer NM24W16
Beschreibung 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect
Hersteller Fairchild
Logo Fairchild Logo 




Gesamt 14 Seiten
NM24W16 Datasheet, Funktion
PRELIMINARY
March 1999
NM24Wxx
2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface
Serial EEPROM with Full Array Write Protect
General Description
The NM24Wxx devices are 2048/4096/8192/16,384 bits, respec-
tively, of CMOS non-volatile electrically erasable memory. These
devices conform to all specifications in the IIC 2-wire protocol and
are designed to minimize device pin count, and simplify PC board
layout requirements.
The entire ememory can be disabled (Write Protected) by con-
necting the WP pin to VCC. The memory then becomes unalterable
unless WP is switched to VSS.
This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by Fairchild's family in 2K,
4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs.
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability and low power consump-
tion.
Features
s Hardware Write Protect for entire memory
s Low Power CMOS
200µA active current typical
10µA standby current typical
1µA standby typical (L)
0.1µA standby typical (LZ)
s IIC Compatible interface
— Provides bidirectional data transfer protocol
s Sixteen byte page write mode
— Minimizes total write time per byte
s Self timed write cycle
— Typical write cycle time of 6ms
s Endurance: 1,000,000 data changes
s Data retention greater than 40 years
s Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
s Available in three temperature ranges
- Commercial: 0° to +70°C
- Extended (E): -40° to +85C
- Automotive (V): -40° to +125°C
Block Diagram
VCC
VSS
WP
SDA
SCL
A2
A1
A0
START
STOP
LOGIC
START CYCLE
H.V. GENERATION
TIMING &CONTROL
SLAVE ADDRESS
REGISTER &
COMPARATOR
CONTROL
LOGIC
LOAD
INC
WORD
ADDRESS
COUNTER
R/W
XDEC
16/
32/
64/
128/
0/1/2/3
4
4
E2PROM
ARRAY
16
YDEC
Device Address Bits
DIN
8
CK
DATA REGISTER
DOUT
© 1999 Fairchild Semiconductor Corporation
NM24Wxx Rev. C.2
1
DS500074-1
www.fairchildsemi.com






NM24W16 Datasheet, Funktion
Device
NM24W02
NM24W04
NM24W08
NM24W16
Address Pins
A0 A1 A2
ADR ADR ADR
NC ADR ADR
NC NC ADR
NC NC NC
Memory Size
2048 Bits
4096 Bits
8192 Bits
16,384 Bits
Number of
Page Blocks
1
2
4
8
ADR is the hardware address (VCC/1 or VSS/0) of the device(s) used.
Pin Descriptions
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out of the
device. It is an open drain output and may be wire–ORed with any
number of open drain or open collector outputs.
Device Operation Inputs (A0, A1, A2)
Device address pins A0, A1, and A2 are connected to VCC or VSS
to configure the EEPROM chip address. Table 1 shows the active
pins across the NM24Wxx device family.
TABLE 1.
Device
NM24W02
NM24W04
NM24W08
NM24W16
A0
ADR
x
x
x
A1
ADR
ADR
x
x
A2 Effects of Addresses
ADR 23 = 8; 8*x(1x2K)**=16K
ADR 22 = 4; 4*x(2x2K)**=16K
ADR 21 = 2; 2*x(4x2K)**=16K
x 20 = 1; 1*x(8x2K)**=16K
* Max # of devices on bus
** Number of page blocks per density
WP Write Protection
If tied to VCC, PROGRAM operations onto memory will not be
executed. (Only READ operations are possible.) If tied to VSS,
normal operation is enabled (READ/WRITE over the entire memory
is possible).
Device Operation
The NM24Wxx supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device that is
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the NM24Wxx will be considered a slave in
all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH are reserved for indicating
start and stop conditions. Refer to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The NM24Wxx
continuously monitors the SDA and SCL lines for the start condi-
tion and will not respond to any command until this condition has
been met.
Stop Condition
All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the NM24Wxx to place the device in the
standby power mode.
ACKNOWLEDGE
Acknowledge is a software convention used to indicate successful
data transfers. The transmitting device, either master or slave, will
release the bus after transmitting eight bits.
During the ninth clock cycle the receiver will pull the SDA line to
LOW to acknowledge that it received the eight bits of data. Refer
to Figure 3.
The NM24Wxx device will always respond with an acknowledge
after recognition of a start condition and its slave address. If both
the device and a write operation have been selected, the NM24Wxx
will respond with an acknowledge after the receipt of each
subsequent eight bit byte.
In the read mode the NM24Wxx slave will transmit eight bits of
data, release the SDA line and monitor the line for an acknowl-
edge. If an acknowledge is detected and no stop condition is
generated by the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further
data transmissions and await the stop condition to return to the
standby power mode.
NM24Wxx Rev. C.2
6 www.fairchildsemi.com

6 Page









NM24W16 pdf, datenblatt
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8 7 65
0.228 - 0.244
(5.791 - 6.198)
1 2 34
Lead #1
IDENT
0.010 - 0.020 x 45°
(0.254 - 0.508)
0.150 - 0.157
(3.810 - 3.988)
8° Max, Typ.
All leads
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.04
(0.102)
All lead tips
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.053 - 0.069
(1.346 - 1.753)
0.014
(0.356)
0.050
(1.270)
Typ
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014 - 0.020 Typ.
(0.356 - 0.508)
8-Pin Molded Small Outline Package (M8)
Package Number M08A
NM24Wxx Rev. C.2
12 www.fairchildsemi.com

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