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82596DX Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer 82596DX
Beschreibung HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
82596DX Datasheet, Funktion
82596DX AND 82596SX
HIGH-PERFORMANCE 32-BIT LOCAL
AREA NETWORK COPROCESSOR
Y Performs Complete CSMA CD Medium
Access Control (MAC) Functions
Independently of CPU
IEEE 802 3 (EOC) Frame Delimiting
Y Supports Industry Standard LANs
IEEE TYPE 10BASE-T (TPE)
IEEE TYPE 10BASE5 (Ethernet )
IEEE TYPE 10BASE2 (Cheapernet)
IEEE TYPE 1BASE5 (StarLAN)
and the Proposed Standard
TYPE 10BASE-F
Proprietary CSMA CD Networks Up
to 20 Mb s
Y On-Chip Memory Management
Automatic Buffer Chaining
Buffer Reclamation after Receipt of
Bad Frames Optional Save Bad
Frames
32-Bit Segmented or Linear (Flat)
Memory Addressing Formats
Y 82586 Software Compatible
Y Optimized CPU Interface
82596DX Bus Interface Optimized to
Intel’s 32-Bit i386TMDX
82596SX Bus Interface Optimized to
Intel’s 16-Bit i386TMSX
Supports Big Endian and Little
Endian Byte Ordering
Y High-Performance 16- 32-Bit Bus
Master Interface
66-MB s Bus Bandwidth
33-MHz Clock Two Clocks Per
Transfer
Bus Throttle Timers
Transfers Data at 100% of Serial
Bandwidth
128-Byte Receive FIFO 64-Byte
Transmit FIFO
Y Network Management and Diagnostics
Monitor Mode
32-Bit Statistical Counters
Y Self-Test Diagnostics
Y Configurable Initialization Root for Data
Structures
Y High-Speed 5-V CHMOS IV
Technology
Y 132-Pin Plastic Quad Flat Pack (PQFP)
and PGA Package
(See Packaging Specifications Order Number 240800-001
Package Type KU and A)
i386TM is a trademark of Intel Corporation
Ethernet is a registered trademark of Xerox Corporation
CHMOS is a patented process of Intel Corporation
Figure 1 82596DX SX Block Diagram
290219 – 1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1996
November 1995
Order Number 290219-006






82596DX Datasheet, Funktion
82596DX SX
Figure 3a 82596DX PGA Pin View Side
290219 – 3
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82596DX pdf, datenblatt
82596DX SX
PIN DESCRIPTIONS (Continued)
Symbol
PQFP
Pin No
Type
Name and Function
PORT 3 I PORT When this signal is received the 82596 latches the data on the
data bus into an internal 32-bit register When the CPU is asserting this
signal it can write into the 82596 (via the data bus) This pin must be
activated twice during all CPU Port access commands
RESET
69
I RESET This active high internally synchronized signal causes the
82596 to terminate current activity The signal must be high for at least
five system clock cycles After five system clock cycles and four TxC
clock cycles the 82596 will execute a Reset when it receives a high
RESET signal When RESET returns to low the 82596 waits for the
first CA signal and then begins the initialization sequence
LE BE
65
I LITTLE ENDIAN BIG ENDIAN This dual-function pin is used to
select byte ordering When LE BE is high little endian byte ordering is
used when low big endian byte ordering is used for data in frames
(bytes) and for control (SCB RFD CBL etc )
CA 119 I CHANNEL ATTENTION The CPU uses this pin to force the 82596 to
begin executing memory resident Command blocks The CA signal is
internally synchronized The signal must be high for at least one
system clock It is latched internally on the high to low edge and then
detected by the 82596
The first CA after a Reset forces the 82596 into the initialization
sequence beginning at location 00FFFFF6h or an SCP address written
to the 82596 using CPU Port access All subsequent CA signals cause
the 82596 to begin executing new command sequences from the SCB
INT INT
125
O INTERRUPT A high signal on this pin notifies the CPU that the 82596
is requesting an interrupt This signal is an edge triggered interrupt
signal and can be configured to be active high or low
VCC 18 Pins (DX)
19 Pins (SX)
POWER a5V g10%
VSS 19 Pins
(DX and SX)
GROUND 0V
TxD 54 O TRANSMIT DATA This pin transmits data to the serial link It is high
when not transmitting
TxC 64 I TRANSMIT CLOCK This signal provides the fundamental timing for
the serial subsystem The clock is also used to transmit data
synchronously on the TxD pin For NRZ encoding data is transferred
to the TxD pin on the high to low clock transition For Manchester
encoding the transmitted bit center is aligned with the low to high
transition Transmit clock should always be running for proper device
operation
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