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82371SB Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer 82371SB
Beschreibung 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
82371SB Datasheet, Funktion
E
82371FB (PIIX) AND 82371SB (PIIX3)
PCI ISA IDE XCELERATOR
n Bridge Between the PCI Bus and ISA Bus
n PCI and ISA Master/Slave Interface
PCI from 25–33 MHz
ISA from 7.5–8.33 MHz
5 ISA Slots
n Fast IDE Interface
Supports PIO and Bus Master IDE
Supports up to Mode 4 Timings
Transfer Rates to 22 MB/Sec
8 x 32-Bit Buffer for Bus Master IDE PCI
Burst Transfers
Separate Master/Slave IDE Mode
Support (PIIX3)
n Plug-n-Play Port for Motherboard Devices
2 Steerable DMA Channels (PIIX Only)
Fast DMA with 4-Byte Buffer (PIIX Only)
2 Steerable Interrupts Lines on the PIIX
and 1 Steerable Interrupt Line on the
PIIX3
1 Programmable Chip Select
n Steerable PCI Interrupts for PCI Device Plug-
n-Play
n PCI Specification Revision 2.1 Compliant
(PIIX3)
n Functionality of One 82C54 Timer
System Timer; Refresh Request;
Speaker Tone Output
n Two 82C59 Interrupt Controller Functions
14 Interrupts Supported
Independently Programmable for
Edge/Level Sensitivity
n Enhanced DMA Functions
Two 8237 DMA Controllers
Fast Type F DMA
Compatible DMA Transfers
7 Independently Programmable
Channels
n X-Bus Peripheral Support
Chip Select Decode
Controls Lower X-Bus Data Byte
Transceiver
n I/O Advanced Programmable Interrupt
Controller (IOAPIC) Support (PIIX3)
n Universal Serial Bus (USB) Host Controller
(PIIX3)
Compatible with Universal Host
Controller Interface (UHCI)
Contains Root Hub with 2 USB Ports
n System Power Management (Intel SMM
Support)
Programmable System Management
Interrupt (SMI)—Hardware Events,
Software Events, EXTSMI#
Programmable CPU Clock Control
(STPCLK#)
Fast On/Off Mode
n Non-Maskable Interrupts (NMI)
PCI System Error Reporting
n NAND Tree for Board-Level ATE Testing
n 208-Pin QFP
The 82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE Xcelerators are multi-function PCI devices
implementing a PCI-to-ISA bridge function and an PCI IDE function. In addition, the PIIX3 implements a
Universal Serial Bus host/hub function. As a PCI-to-ISA bridge, the PIIX/PIIX3 integrates many common I/O
functions found in ISA-based PC systems—a seven-channel DMA controller, two 82C59 interrupt controllers,
an 8254 timer/counter, and power management support. In addition to compatible transfers, each DMA
channel supports type F transfers. Chip select decoding is provided for BIOS, real time clock, and keyboard
controller. Edge/Level interrupts and interrupt steering are supported for PCI plug and play compatibility. The
PIIX/PIIX3 supports two IDE connectors for up to four IDE devices providing an interface for IDE hard disks
and CD ROMs. The PIIX/PIIX3 provides motherboard plug and play compatibility. PIIX implements two
steerable DMA channels (including type F transfers) and up to two steerable interrupt lines. PIIX3 implements
one steerable interrupt line. The interrupt lines can be routed to any of the available ISA interrupts. Both
PIIX/PIIX3 implement a programmable chip select.
PIIX3 contains a Universal Serial Bus (USB) Host Controller that is UHCI compatible. The Host Controller’s
root hub has two programmable USB ports. PIIX3 also provides support for an external IOAPIC.
This document describes the PIIX3 Component. Unshaded areas describe the 82371FB PIIX. Shaded areas,
like this one, describe the PIIX3 operations that differ from the 82371FB PIIX.
© INTEL CORPORATION 1996, 1997
April 1997
Order Number: 290550-002






82371SB Datasheet, Funktion
82371FB (PIIX) AND 82371SB (PIIX3)
E
3.1. Memory and I/O Address Map ........................................................................................................... 89
3.1.1. I/O Accesses ............................................................................................................................... 89
3.1.2. Memory Address Map ................................................................................................................. 89
3.1.3. BIOS MEMORY........................................................................................................................... 90
3.2. PCI Interface ...................................................................................................................................... 90
3.2.1. TRANSACTION TERMINATION ................................................................................................. 90
3.2.2. PARITY SUPPORT ..................................................................................................................... 91
3.2.3. PCI ARBITRATION ..................................................................................................................... 91
3.3. ISA Interface ...................................................................................................................................... 92
3.4. DMA Controller................................................................................................................................... 93
3.4.1. TYPE F TIMING .......................................................................................................................... 94
3.4.2. ISA REFRESH CYCLES ............................................................................................................. 94
3.5. PCI Local Bus IDE ............................................................................................................................. 95
3.5.1. ATA REGISTER BLOCK DECODE ............................................................................................. 96
3.5.2. ENHANCED TIMING MODES ..................................................................................................... 97
3.5.2.1. Back-To-Back PIO IDE Transactions.................................................................................... 98
3.5.2.2. IORDY Masking .................................................................................................................... 98
3.5.2.3. PIO 32 Bit IDE Data Port Mode ............................................................................................ 98
3.5.3. BUS MASTER FUNCTION.......................................................................................................... 98
3.6. Universal Serial Bus Host Controller (PIIX3 only) ............................................................................. 100
3.7. Interval Timer ................................................................................................................................... 102
3.8. Interrupt Controller ........................................................................................................................... 103
3.8.1. PROGRAMMING THE ICWs/OCWs ......................................................................................... 104
3.8.2. EDGE AND LEVEL TRIGGERED MODE .................................................................................. 104
3.8.3. INTERRUPT STEERING........................................................................................................... 104
3.9. Stand-Alone IOAPIC Support (PIIX3) ............................................................................................... 105
3.10. INTR Signaling with Pentium® processor Local APIC in Virtual Wire Mode ................................... 106
3.11. X-Bus Peripheral Support............................................................................................................... 107
3.12. Power Management ....................................................................................................................... 108
3.12.1. SMM MODE ............................................................................................................................ 109
3.12.2. SMI SOURCES ....................................................................................................................... 109
3.12.3. CLOCK CONTROL.................................................................................................................. 110
3.13. Reset Support ................................................................................................................................ 110
3.13.1. HARDWARE STRAPPING OPTIONS ..................................................................................... 111
4.0. PINOUT AND PACKAGE INFORMATION .......................................................................................... 112
4.1. Pinout............................................................................................................................................... 112
4.2. PACKAGE DIMENSIONS ................................................................................................................ 117
5.0. TESTABILITY (PIIX/PIIX3) .................................................................................................................. 118
5.1. Test Mode Description ..................................................................................................................... 118
5.2. NAND Tree Mode............................................................................................................................. 118
5.3. Tri-state Mode.................................................................................................................................. 122
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82371SB pdf, datenblatt
82371FB (PIIX) AND 82371SB (PIIX3)
E
Signal Name
IORDY
SOE#
SDIR
Type
I
O
O
Description
IO CHANNEL READY: This input signal is directly driven by the
corresponding signal on up to two IDE connectors (primary and
secondary).
SYSTEM ADDRESS TRANSCEIVER OUTPUT ENABLE: This signal
controls the output enables of the ’245 transceivers that interface the
DD[15:0] signals to the SA[19:8], SBHE#, PCS# and APICCS# (PIIX3
only) signals.
SYSTEM ADDRESS TRANSCEIVER DIRECTION: This signal controls
the direction of the ’245 transceivers that interface the DD[15:0] signals
to the SA[19:8], SBHE#, PCIS, and APICCS# (PIIX3 only), signals.
Default condition is high (transmit). When an ISA Bus master is granted
use of the bus, the transceivers are turned around to drive the ISA
address [19:8] on DD[15:3]. The address can then be latched by the
PIIX/PIIX3. In this case, the SDIR signal is low (receive). The SOE# and
SDIR signals taken together as a group can assume one of three states:
SOE# SDIR State
01
11
00
PCI to ISA transaction
PCI to IDE
ISA Bus master
Signals Buffered from LA[23:17]
These signals are buffered from the LA[23:17] lines by an ALS244 tri-state buffer. The output enable of this
buffer is tied asserted. These signals are set up with respect to the IDE command strobes (DIOR# and IOW#)
and are valid throughout I/O transactions targeting the ATA register block(s).
Signal Name
LA23/
CS1S
Type
I/O
LA22/
CS3S
I/O
LA21/
CS1P
I/O
LA20/
CS3P
I/O
LA[19:17]
DA[2:0]
I/O
Description
CHIP SELECT: CS1S is for the ATA command register block and
corresponds to the inverted CS1FX# on the secondary IDE connector.
CS1S is inverted externally (see PCI Local Bus IDE section).
CHIP SELECT: CS3S is for the ATA control register block and
corresponds to the inverted CS3FX# on the secondary IDE connector.
CS3S is inverted externally (see PCI Local Bus IDE section).
CHIP SELECT: CS1P is for the ATA command register block and
corresponds to the inverted CS1FX# on the primary IDE connector. CS1P
is inverted externally (see PCI Local Bus IDE section).
CHIP SELECT: CS3P is for the ATA control register block and
corresponds to the inverted CS3FX# on the primary IDE connector. CS3P
is inverted externally (see PCI Local Bus IDE section).
DISK ADDRESS: DA[2:0] are used to indicate which byte in either the
ATA command block or control block is being addressed.
12

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