|
|
PDF ML65L244CK Data sheet ( Hoja de datos )
| Número de pieza | ML65L244CK | |
| Descripción | High Speed Dual Quad Buffer/Line Drivers | |
| Fabricantes | Micro Linear | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ML65L244CK (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
|
No Preview Available !
August 1996
ML65244/ML65L244*
High Speed Dual Quad Buffer/Line Drivers
GENERAL DESCRIPTION
The ML65244 and ML65L244 are non-inverting dual quad
buffer/line drivers. The high operating frequency (50MHz
driving a 50pF load) and low propagation delay
(ML65244 – 1.7ns, ML65L244 – 2ns) make them ideal for
very high speed applications such as processor bus
buffering and cache and main memory control.
These buffers use a unique analog implementation to
eliminate the delays inherent in traditional digital designs.
Schottky clamps reduce under and overshoot, and special
output driver circuits limit ground bounce. The ML65244
and ML65L244 conform to the pinout and functionality of
the industry standard FCT244 and are intended for
applications where propagation delay is critical to the
system design.
Note: This part was previously numbered ML6582.
FEATURES
s Low propagation delay — 1.7ns ML65244
2.0ns ML65L244
s Fast Dual 4-bit TTL level buffer/line driver with tri-state
capability on the output (two 4-bit sections)
s TTL compatible input and output levels
s Schottky diode clamps on all inputs to handle
undershoot and overshoot
s Onboard schottky diodes minimize noise
s Reduced output swing of 0 – 4.1 volts
s Ground bounce controlled outputs, typically less
than 400mV
s Industry standard FCT244 type pinout
s Applications include high speed cache memory, main
memory, processor bus buffering, and graphics cards
BLOCK DIAGRAM
*This Part Is Obsolete
VCC YAO
BO YA1
B1
YA2
B2 YA3 B3
20 18 17 16 15 14 13 12 11
2G 19
VCC
1G 1
10 2 3 4 5 6 7 8 9
GND AO
YBO
A1
YB1
A2
YB2 A3 YB3
1
1 page  
FUNCTIONAL DESCRIPTION
The ML65244 and ML65L244 are very high speed non-
inverting buffer/line drivers with three-state outputs which
are ideally suited for bus-oriented applications. They
provide a low propagation delay by using an analog
design approach (a high speed unity gain buffer), as
compared to conventional digital approaches. The
ML65244 and ML65L244 follow the pinout and
functionality of the industry standard FCT244 series of
buffer/line drivers and are intended to replace them in
designs where the propagation delay is a critical part of
the system design considerations. The ML65244 and
ML65L244 are capable of driving load capacitances
several times larger than their input capacitance. They are
configured so that the Ai inputs go to the YAi outputs, with
the A side output enable controlled by 1G. Similarly, 2G
controls the Bi inputs which go to the YBi outputs.
These unity gain analog buffers achieve low propagation
delays by having the output follow the input with a small
offset. The output rise and fall times will closely match
those of the input waveform. All inputs and outputs have
Schottky clamp diodes to handle undershoot or overshoot
noise suppression in unterminated applications. All
outputs have ground bounce suppression (typically
< 400mV), high drive output capability with almost
immediate response to the input signal, and low
output skew.
The IOL current drive capability of a buffer/line driver is
often interpreted as a measure of its ability to sink current
in a dynamic sense. This may be true for CMOS buffer/
ML65244/ML65L244
line drivers, but it is not true for the ML65244 and
ML65L244. This is because their sink and source current
capability depends on the voltage difference between the
output and the input. The ML65244 can sink or source
more than 100mA to a load when the load is switching
due to the fact that during the transition, the difference
between the input and output is large. IOL is only
significant as a DC specification, and is 25mA.
ARCHITECTURAL DESCRIPTION
Until now, buffer/line drivers have been implemented in
CMOS logic and made to be TTL compatible by sizing the
input devices appropriately. In order to buffer large
capacitances with CMOS logic, it is necessary to cascade
an even number of inverters, each successive inverter
larger than the preceding, eventually leading to an inverter
that will drive the required load capacitance at the
required frequency. Each inverter stage represents an
additional delay in the gating process because in order for
a single gate to switch, the input must slew more than half
of the supply voltage. The best of these CMOS buffers has
managed to drive a 50pF load capacitance with a delay of
3.2ns. Micro Linear has produced a dual quad buffer/line
driver with a delay less than 1.7ns by using a unique
circuit architecture that does not require cascaded logic
gates. The ML65244 uses a feedback technique to
produce an output that follows the input. If the output
voltage is not close to the input, then the feedback
circuitry will source or sink enough current to the load
capacitance to correct the discrepancy.
VCC
R8
Q1
R3
R1
IN
Q3
R4
Q4
R5
Q5
R2
Q6
R6
Q2
R7
OUT
Q7
GND
Figure 5. One buffer cell of the ML65244
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet ML65L244CK.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ML65L244CK | High Speed Dual Quad Buffer/Line Drivers | Micro Linear |
| ML65L244CS | High Speed Dual Quad Buffer/Line Drivers | Micro Linear |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |