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PDF ML6553 Data sheet ( Hoja de datos )
| Número de pieza | ML6553 | |
| Descripción | Bus Termination Regulator | |
| Fabricantes | Fairchild | |
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ML6553
Bus Termination Regulator
www.fairchildsemi.com
Features
• Can source and sink up to 1A
• Generates termination voltages for DDR SDRAM,
SSTL_2 SDRAM, SGRAM, or equivalent memories
• Generates termination voltages for active termination
schemes for GTL+, DDR, Rambus™, VME, LV-TTL,
PECL and other high speed logic
• VL regulated to within 3% at 800mA
• Minimum external components. Requires no feedback
compensation
• Fixed frequency operation for easier system integration
• Lower power consumption than passive, resistor divider
termination, reducing heat by as much as 50%
• Separate voltages for VCCQ and PVDD
General Description
The ML6553 switching regulator is designed to convert
voltage supplies ranging from 2.0V to 3.6V into a desired
output voltage or termination voltage for various applica-
tions. The ML6553 can be implemented to produce
regulated output voltages in two different modes. In the
default mode, the output is 50% of voltage applied to VCCQ.
The switching regulator is capable of sourcing or sinking up
to 1A of current.
The ML6553, used in conjunction with series termination
resistors, provides an excellent voltage source for active
termination schemes of high speed transmission lines as
those seen in high speed memory buses and distributed back-
plane designs. The voltage output of the regulator can be
used as a termination voltage for other bus interface
standards such as SSTL, DDR, Rambus™, GTL+, VME,
LV-CMOS, LV-TTL, P-ECL, and CMOS.
Block Diagram
1
VCCQ
4
AVCC
CLK
190kΩ
OSCILLATOR/
RAMP GENERATOR RAMP
VCCQ/2
2
BUFFER
–
+
AGND
3
190kΩ
+ VINTEG
–
SQ
–
RQ
+
PWM
COMPARATOR
5
PVDD
Q1
VL
6
VL
7
Q2
DGND
8
REV. 1.0.2 3/21/01
1 page  
PRODUCT SPECIFICATION
ML6553
Design Consideration
Inductor Selection
The ML6553 requires the selection of an external inductor.
A value of 4.7µH is a good choice, but any value between
2.2µH and 10µH is acceptable. Choosing an inductance
value of less than 2.2µH will reduce the component’s foot-
print or the DC resistance, but the output voltage ripple will
increase. Conversely, inductance values greater than 10µH
will reduce the output ripple, but component size and output
regulation become issues.
It is important to use an inductor that is rated to handle 1.5A
peak currents without saturating. Also look for an inductor
with low winding resistance. An inductor with low winding
resistance leads to better regulation and higher output current
capability. A good rule of thumb is to use inductors with
20mΩ or less of winding resistance.
The final selection of the inductor will be based on trade-offs
between size, cost and performance. Make your selections
carefully. Inductor tolerance, core and copper loss will vary
with the type of inductor selected and should be evaluated
with the ML6553 under worst case conditions to determine
its suitability.
Suggested inductor for L1:
Manufacturer Part No.
Coiltronics UP3-4R7
DC
Inductance Resistance
4.7µH 0.011Ω
Coiltronics (561) 241-7876
Output Capacitor
The output capacitor filters the pulses of current from the bus
terminator regulator as well as lowers the AC output imped-
ance. For the best performance, one 330µF OS-CON decou-
pling capacitor is recommended.
Note that data transitions on the bus cause fast changes in
output current. These fast current changes cause high
frequency spikes to appear on the output. To minimize these
effects, choose an output capacitor with a combined ESR of
less than 50mΩ and use good layout practices to minimize
trace inductance from the output capacitors to the termina-
tion resistors. In addition, it is also recommended to bypass
the termination resistors with 0.01µF ceramic capacitors.
Suitable capacitors can be obtained from the following
vendors:
AVX
Sanyo
(207) 282-5111
(619) 661-6835
TPS Series
OS-CON Series
Input Capacitor
It is recommended to de-couple the PVDD input with a 47µF
to 100µF capacitor. This provides the benefits of preventing
the input ripple from affecting the ML6553 control circuitry,
as well as improves the efficiency by reducing the I squared
R losses during the charge cycle of the inductor. Again, a low
ESR capacitor (such as tantalum) is recommended.
The AVCC input should be de-coupled with at least a
ceramic capacitor but a low pass RC filter is recommended if
the supply is particularly noisy. If a RC filter is used, the
series resistor value needs to low enough to prevent exces-
sive voltage drops and high enough to provide effective
filtering. Resistor values on the order of 100Ω are accept-
able.
The VCCQ pin can also be bypassed with a ceramic capacitor
if noise is present. The VCCQ pin can be de-coupled with a
low pass RC filter if there is significant noise pickup on its
input. If a RC filter is used, resistor values on the order of
1,000Ω are acceptable.
Layout
Good layout practices will ensure the proper operation of the
ML6553. Some layout guidelines follow:
• Use adequate ground and power traces or planes.
• Keep the 47µF-100µF input capacitor as close to PVDD
and DGND as possible.
• Use short trace lengths from the inductor to the VL pins
and from the inductor to the output capacitors.
• Use a separate trace from AGND to DGND, and use
DGND as the ground point for all the power components.
• Use additional bypass capacitors at each termination
resistor pack.
A typical application circuit schematic is shown in Figure 2,
and a sample layout is shown in Figure 3.
IOUT(MAX) = -(--D-----E----S----I--R-----E----D-----O---L-V--D-A---C--–--R--O---+---U-0---T-.-0--P--2---U0----T----O----V----A---)----×----V-----T---T- (1)
Where LDCR is the DC resistance of the output inductor, L1
in Figure 2, and 0.020 is the source resistance of the output
VL. Both LDCR and 0.020 are in Ohms.
REV. 1.0.2 3/21/01
5
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