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PDF ML65245CK Data sheet ( Hoja de datos )
| Número de pieza | ML65245CK | |
| Descripción | High Speed Octal Buffer Transceivers | |
| Fabricantes | Micro Linear | |
| Logotipo |  |
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August 1996
ML65245**/ML65L245*
High Speed Octal Buffer Transceivers
GENERAL DESCRIPTION
The ML65245 and ML65L245 are non-inverting octal
transceivers. The high operating frequency (50MHz
driving a 50pF load) and low propagation delay
(ML65245 – 1.7ns, ML65L245 – 2ns) make them ideal for
very high speed applications such as processor bus
buffering and cache and main memory control.
These transceivers use a unique analog implementation to
eliminate the delays inherent in traditional digital designs.
Schottky clamps reduce under and overshoot, and special
output driver circuits limit ground bounce. The ML65245
and ML65L245 conform to the pinout and functionality of
the industry standard FCT245 and are intended for
applications where propagation delay is critical to the
system design.
Note: This part was previously numbered ML6580.
FEATURES
s Low propagation delay — 1.7ns ML65245
2.0ns ML65L245
s Fast 8-bit TTL level transceiver with three-state
capability on the output
s TTL compatible input and output levels
s Schottky diode clamps on all inputs to handle
undershoot and overshoot
s Onboard schottky diodes minimize noise
s Reduced output swing of 0 – 4.1 volts
s Ground bounce controlled outputs, typically less
than 400mV
s Industry standard FCT245 type pinout
s Applications include high speed cache memory, main
memory, processor bus buffering, and graphics cards
** This Product Is End Of Life As Of August 1, 2000
* This Product Is Obsolete
BLOCK DIAGRAM
VCC A0
A1
A2
A3 A4
A5
A6 A7
20 2
3
4
56
7
89
T/R 1
VCC
OE 19
10 18
17
16
15 14
13 12 11
GND B0
B1
B2 B3 B4 B5
B6 B7
1
1 page  
FUNCTIONAL DESCRIPTION
The ML65245 and ML65L245 are very high speed non-
inverting transceivers with three-state outputs which are
ideally suited for bus-oriented applications. They provide
a low propagation delay by using an analog design
approach (a high speed unity gain buffer), as compared to
conventional digital approaches. The ML65245 and
ML65L245 follow the pinout and functionality of the
industry standard FCT245 series of transceivers and are
intended to replace them in designs where the
propagation delay is a critical part of the system design
considerations. The ML65245 and ML65L245 are capable
of driving load capacitances several times larger than their
input capacitance. They are configured so that signals
pass from Ai to Bi, or from Bi to Ai, depending on the state
of the T/R pin. All of the signal lines can be made high
impedance via the OE pin.
These unity gain analog buffers achieve low propagation
delays by having the output follow the input with a small
offset. The output rise and fall times will closely match
those of the input waveform. All inputs and outputs have
Schottky clamp diodes to handle undershoot or overshoot
noise suppression in unterminated applications. All
outputs have ground bounce suppression (typically
< 400mV), high drive output capability with almost
immediate response to the input signal, and low output
skew.
The IOL current drive capability of a buffer/line driver is
often interpreted as a measure of its ability to sink current
ML65245**/ML65L245*
in a dynamic sense. This may be true for CMOS buffer/
line drivers, but it is not true for the ML65245 and
ML65L245. This is because the their sink and source
current capability depends on the voltage difference
between the output and the input. The ML65245 can sink
or source more than 100mA to a load when the load is
switching due to the fact that during the transition, the
difference between the input and output is large. IOL is
only significant as a DC specification, and is 25mA.
ARCHITECTURAL DESCRIPTION
Until now, buffer/line drivers have been implemented in
CMOS logic and made to be TTL compatible by sizing the
input devices appropriately. In order to buffer large
capacitances with CMOS logic, it is necessary to cascade
an even number of inverters, each successive inverter
larger than the preceding, eventually leading to an inverter
that will drive the required load capacitance at the
required frequency. Each inverter stage represents an
additional delay in the gating process because in order for
a single gate to switch, the input must slew more than half
of the supply voltage. The best of these CMOS buffers has
managed to drive a 50pF load capacitance with a delay of
3.2ns. Micro Linear has produced an octal transceiver
with a delay less than 1.7ns by using a unique circuit
architecture that does not require cascaded logic gates.
The ML65245 uses a feedback technique to produce an
output that follows the input. If the output voltage is not
close to the input, then the feedback circuitry will source
or sink enough current to the load capacitance to correct
the discrepancy.
VCC
R8
Q1
R3
R1
IN
Q3
R4
Q4
R5
Q5
R2
Q6
R6
Q2
R7
OUT
Q7
GND
Figure 5. One buffer cell of the ML65245
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet ML65245CK.PDF ] | |
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